Statistical Distribution of Defect Parameters

Kaczer, B.; Toledano-Luque, M.; Franco, J.; Weckx, Pieter

doi:10.1007/978-1-4614-7909-3_7

Cited by 8 publications

(6 citation statements)

References 22 publications

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“…where t inv is the oxide thickness corresponding to capacitance in inversion, A the area of the device channel, and N A the channel doping, with the exponent α has been observed to be around 0.5 in simulations [13]. In order to test Eq.…”

Section: Trap Impact On Fet Propertiesmentioning

confidence: 97%

“…Note that while the majority of charged traps results in small ΔV th 's, a small fraction of traps will significantly change V th by up to tens of mV [12]. The average impact of a single defect η on the threshold voltage is a fundamental parameter determining the variability of deeply scaled technologies [13]. The time-dependent variance of the threshold voltage shifts of a population of devices (such as e.g.…”

Section: Trap Impact On Fet Propertiesmentioning

confidence: 99%

“…where 〈∆V th 〉 is the average threshold voltage shift due to BTI [13,14]. Because of the similarities between BTI and Random Telegraph Noise (RTN) [12], this parameter also reflects the average expected amplitude of the RTN signal in deeply-scaled devices [14].…”

Section: Trap Impact On Fet Propertiesmentioning

confidence: 99%

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Experimental characterization of BTI defects

Kaczer

Afanas’ev

Rott

et al. 2013

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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Selected physical and electrical characterization of gate-oxide defects is reviewed. Interfacial dangling bond defects at interfaces of Si and SiGe are characterized electrically and compared to the electron spin resonance data. It is found that additional silicon dangling bonds (P b0 -ceters) acting as amphoteric interface traps are generated upon oxygen scavenging anneal. A close density of P b0 centers is also found in Si/SiGe/Si/HfO 2 stack. The Ge dangling bond defects (Ge P b1 centers) found at interfaces of SiGe with thermal SiO 2 are shown to behave as acceptor centers. The properties of individual gate-oxide defects in FETs are studied with TimeDependent Defect Spectroscopy (TDDS), an electrical characterization technique. The primary properties of a defect are its capture and emission time constants, both dependent on the local electric gate field and the temperature. Considering the wide distributions of these defect properties, complete characterization of many defects is required over the full gate and drain voltage range from 0 to VDD at different temperatures. This is desirable in order to model degradation for large, "analog" FETs and to model the ΔV th -variability of deeply-scaled FETs. The impact of individual charged defects on transistor properties is then discussed. It is shown that the shift in the threshold voltage is exponentially distributed, with a small fraction of defects causing significant shifts of tens of mV. The average impact per charged defect is experimentally confirmed to be increasing with the gate oxide thickness, the substrate doping, and with the decreasing FET area. The average impact per charged defect is found to be reduced in SiGe substrates, contributing to lower degradation of SiGebased FETs.In low-doped substrates, other sources of variability, such as interface states, are shown to take over. The impact of a single charged gate-oxide defect on the full I-V characteristic is measured and corroborated by atomistic device simulations, thus enabling the path to compact modeling of degraded deeply-scaled FET devices. Finally, the model explaining the correlation between drain and gate current RTN is discussed.

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Section: Trap Impact On Fet Propertiesmentioning

confidence: 97%

Section: Trap Impact On Fet Propertiesmentioning

confidence: 99%

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Experimental characterization of BTI defects

Kaczer

Afanas’ev

Rott

et al. 2013

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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“…Additionally, seemly identical device may exhibit a different number of traps (assumed to be Poisson distributed) and the properties of each trap are random (e.g. ∆I d is considered exponentially distributed [10]- [13] and τ log-uniformly distributed). Hence, each device has a different RTN behavior.…”

Section: Random Telegraph Noisementioning

confidence: 99%

“…The figure shows that traps much faster than the integration period have a negligible effect on delay variance and only traps with an energy around the Fermi-level have a significant contribution to delay variance. From (10), the contribution of traps much slower than t delay (τ >> t delay ) to the variance is given by…”

Section: Uncertainty Of the Propagation Delay In An Inverter Due To Rtnmentioning

confidence: 99%

Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators

Silva

Both

Wirth

2022

IEEE J. Electron Devices Soc.

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In highly scaled MOSFETs, random telegraph noise (RTN) can decrease the reliability and yield of circuits. RTN is produced by charge trapping, which in large devices results in 1/f noise. We derived analytical formulations for modeling the impact of RTN in the delay of inverters and in the jitter of ring oscillators. We show that the parameters of interest when characterizing RTN for circuit analysis are the distribution of current deviations and the density of traps in the space of area, energy and in log-space of time-constants. The model gives a direct relation between jitter variance in oscillators (or delay variance in inverters) and the power spectral density of RTN, which includes 1/f noise. The formulations can be written using time-or frequency-domain parameters.

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NBTI in (Si)Ge Channel Devices

Franco¹,

Kaczer²

2013

Bias Temperature Instability for Devices and Circuits

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Statistical Distribution of Defect Parameters

Cited by 8 publications

References 22 publications

Experimental characterization of BTI defects

Experimental characterization of BTI defects

Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators

NBTI in (Si)Ge Channel Devices

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