Statistical Criticality Computation Using the Circuit Delay

Abstract

The statistical nature of gate delays in current day technologies necessitates the use of measures, such as path criticality and node/edge criticality for timing optimization. Node criticalities are typically computed using the complementary path delay. An alternative approach to compute the criticality using the circuit delay has been recently proposed. In this paper, we discuss in detail, the use of circuit delay to compute node criticalities and show that the criticality thus found is not equal to the conventional measure found using complementary path delay. However, there is a monotonic relationship between them and the two measures can be used interchangeably. We derive new bounds for the global criticality and propose a pruning algorithm based on these bounds to improve the accuracy and speed of computation. The use of this pruning technique results in a significant speedup in criticality computations. We obtain an order of magnitude average speedup for ISCAS benchmarks.

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

“…Each gate of the circuit is annotated with its criticality. The criticalities in this example are computed using the method proposed in [28].…”

“…Each gate of the circuit is annotated with its criticality. The criticalities in this example are computed using the method proposed in [28]. As it can be seen, gate g 3 has the largest criticality and it will be the first candidate of the optimisation algorithm.…”

“…In order to compute AC, we need to compute the criticality of each gate. Without loss of generality, the incremental criticality computation method introduced in [21, 28] is used to find the criticality of each gate. However, any of the similar methods can be adapted to the proposed algorithm.…”

“…In order to obtain specialised information for steering statistical optimisation, characteristic metrics have been introduced [6, 13–35]. Yield gradient (YG) which is an effective sensitivity metric for guiding the statistical timing optimisation flow is defined as the change in the timing yield (TY) of the circuit for small changes in the size of the gates [19, 24].…”

“…the maximum delay of all paths which are not going through that node/edge. In order to overcome the error induced by max operator in criticality computation, a criticality computation method using unary and conditional operator is introduced in [28]. In [22, 29], an incremental criticality computation using circuit delay is introduced.…”