Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

Abstract

Abstract-The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. Besides proposing a linear programming model for small systems, a novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.

Energy Efficiency on Multi-Core Architectures with Multiple Voltage Islands

“…The difference between EOH (in this paper) and the algorithm presented in [13], is that we map one task set to one core, instead of just one task per core; and that we do not consider the energy consumed for communication between tasks, thus our fitness functions are simplified. Although EOH may help to improve the solutions, in the worst cases, the quality of the solution remains as the initial solution.…”

“…It also describes an algorithm extended from [13], based on extremal optimization. These three algorithms have low time complexity but derive non-optimal solutions.…”

“…Extremal Optimization Heuristic (EOH): This algorithm, extended from [13], performs a random search to improve the energy consumption, starting from an arbitrary initial solution, e.g., CCH. The algorithm is based on swapping, by selecting two task sets to swap per iteration: an unfavourable task set and a replacement task set.…”

“…To the best of our knowledge, there is little research regarding multicore architectures with multiple voltage islands when the hardware platform is fixed, i.e., when the number of voltage islands is not decided based on the applications. The closest research for mapping can be found in [13], where the Extremal Optimization meta-heuristic is applied to solve a similar problem. In [13], a task graph and communication costs between cores are considered, but only one task can be assigned to each core and no theoretical analysis for performance is provided.…”

“…The closest research for mapping can be found in [13], where the Extremal Optimization meta-heuristic is applied to solve a similar problem. In [13], a task graph and communication costs between cores are considered, but only one task can be assigned to each core and no theoretical analysis for performance is provided.…”