Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

Singh, Rahul; Hong, Gi-Moon; Kim, Mino; Park, Jihwan; Shin, Woo Young; Kim, Suhwan

doi:10.1016/j.vlsi.2011.11.013

Cited by 8 publications

(13 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Removing redundant switching at the output node was the objective of previously proposed True single phase clock domino logic (TSPC) [9], [10], limited switch dynamic logic (LSDL) [11], [12] and pseudo dynamic buffer (PDB) [13]. Single-phase SP-domino logic [14] and static switching pulse domino logic techniques [15] are proposed to control the redundant switching both at dynamic and output nodes.…”

Section: (4)mentioning

confidence: 99%

“…SSPD multiplexors also have the static input and output characteristics [15]. SP-Domino multiplexors use single transistor as pull up and keeper but in case of SSPD multiplexors employ separate transistors M1 and M2.…”

Section: Static Switching Pulse Domino (Sspd) Multiplexormentioning

confidence: 99%

“…To reduce the redundant switching only at output node true single phase clock domino logic (TSPC) [9], [10], limited switch dynamic logic (LSDL) [11], [12] and pseudo dynamic buffer (PDB) [13] are given in the literature. To reduce the redundant switching at both dynamic and output nodes Single-phase SP-domino logic [14] and static switching pulse domino logic [15] are given in the literature. The Single-phase SP-domino multiplexors are inflexible as they use the same transistor as pull up and keeper.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Mishra¹,

Modanwal²

2017

IJCA

View full text Add to dashboard Cite

In wide fan-in domino multiplexors, significant power losses are introduced due to the high switching activity at both dynamic and output nodes. In this paper a multiplexor is proposed with static switching at both dynamic and output nodes. This technique has a control pulse generator circuit which turns on the pull up transistor conditionally for a short duration only. This technique is advanced than previously existing techniques as it has faster response over other existing techniques but lesser power consumption and lesser area required. Simulation is done using 0.18µm CMOS technology. Power consumption of proposed multiplexor is calculated and the results are compared with existing multiplexors for different loading condition, clock frequency and temperature. For capacitance 100 fF, proposed domino multiplexor circuit reduces power consumption by 81.08%, 17.57% and 25.50% as compared to standard footless domino, SP-Domino and SSPD multiplexors.

show abstract

Section: (4)mentioning

confidence: 99%

Section: Static Switching Pulse Domino (Sspd) Multiplexormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Mishra¹,

Modanwal²

2017

IJCA

View full text Add to dashboard Cite

show abstract

“…Static switching mechanisms have also been employed in domino logic circuits to reduce the transitions at the output node. This reduces the dynamic power dissipation and hence the total power consumption [20][21][22][23]. The modification of a domino logic circuit aims at improving the robustness and speed performance of the circuit [24][25][26][27][28][29].…”

Section: Introductionmentioning

confidence: 99%

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Angeline

Bhaaskaran

2019

ETRI Journal

View full text Add to dashboard Cite

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

show abstract

“…Different circuits are proposed in the literature to deal this issue. Single phase domino logic [6] and static switching pulse domino [7] logic reduces the redundant switching at both dynamic and output node. True single phase clock domino logic (TSPC) [8], [9], limited switch dynamic logic (LSDL) [10] and pseudo dynamic buffer (PDB) [11] reduces the redundant switching only at output node.…”

Section: Introductionmentioning

confidence: 99%

Conditional Precharge Dynamic Buffer Circuit

Pandey¹,

Mishra²,

Mishra³

et al. 2012

IJCA

View full text Add to dashboard Cite

In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuit and compared the results with existing circuits for different logic function, loading condition, clock frequency, temperature and power supply. For capacitance 500fF, our proposed circuit reduces power consumption by 72.69%, 26.35% and 24.03% as compared to standard footless domino, SP-Domino and SSPD techniques.

show abstract

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers

Cited by 8 publications

References 17 publications

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Conditional Precharge Dynamic Buffer Circuit

Contact Info

Product

Resources

About