Static RAMs with microwatt data retention capability

Dumbri, A.C.; Rosenzweig, W.

doi:10.1109/jssc.1980.1051478

Cited by 2 publications

(1 citation statement)

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“…If the NMOS pull-down transistors can be turned off better than one teraohm, the cell can retain data. Picowatt standby power per bit can be realized with such cells [106]. A perturbation on node N 2 in figure 2(a) (assumed 'low' initially) is counteracted by a large available current difference from the two FETs of the inverter that drives N 2 .…”

Section: Random Access Memory Cellsmentioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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Section: Random Access Memory Cellsmentioning

confidence: 99%