Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs

Abstract

SUMMARYThis paper studies the static mapping of multiple applications on embedded many-core SoCs. The mapping techniques proposed in this paper take into account both inter-application and intra-application parallelism in order to fully utilize the potential parallelism of the manycore architecture. Two approaches are proposed for static mapping: one approach is based on integer linear programming and the other is based on a greedy algorithm. Experiments show the effectiveness of the proposed techniques.

Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs

“…For such embedded systems, we studied static and exclusive application mapping of multiple data-parallel applications [6]. In our previous research, applications are exclusively mapped onto cores shown in Fig.…”

“…In this paper, we propose two static application mapping, which allows the dynamic application switching, including an ILP-based technique and a greedy algorithm. Contribution of this research is to loose the mapping constraints from previous research [6]. This paper proposes the new mapping techniques to support dynamic application switching such that two applications share the same cores.…”

“…Figure 2 and Fig. 3 show execution example of exclusive mapping [6] and mapping supporting dynamic application switching proposed in this paper, respectively. X-axis means the execution time, and Y-axis means the core ID.…”

“…However, when specific applications are guaranteed to be never executed in parallel, these applications can share the same cores. This is a big opportunity to improve CPU utilization, but previous research [6] does not take into account this opportunity at all. The dynamic application switching proposed in this paper exploits the opportunity to share the same cores.…”

“…Since Tile 1 and Tile 5 are overlapped, overlap 1,5 and overlap 5,1 take 1. On the other hand, overlap 1,6 and overlap 6,1 take 0 because Tile 1 and Tile 6 do not share any cores. We also assume four applications, and gain i, j and parallel i1,i2 are defined in Table 2 and Table 3.…”