Static Compilation Analysis for Host-Accelerator Communication Optimization

Abstract

Abstract. We present an automatic, static program transformation that schedules and generates ecient memory transfers between a computer host and its hardware accelerator, addressing a well-known performance bottleneck. Our automatic approach uses two simple heuristics: to perform transfers to the accelerator as early as possible and to delay transfers back from the accelerator as late as possible. We implemented this transformation as a middle-end compilation pass in the pips/Par4All compiler. In the generated code, redundant communications due to data reuse between kernel executions are avoided. Instructions that initiate transfers are scheduled eectively at compile-time. We present experimental results obtained with the Polybench 2.0, some Rodinia benchmarks, and with a real numerical simulation. We obtain an average speedup of 4 to 5 when compared to a naïve parallelization using a modern gpu with Par4All, hmpp, and pgi, and 3.5 when compared to an OpenMP version using a 12-core multiprocessor.

Scaling large-data computations on multi-GPU accelerators

“…It creates opportunities for such overlap by transforming the computation into multiple chunks and transferring the data for chunk '(i+1)' while executing chunk 'i'. Our technique contrasts with those that reduce data transfer overhead by eliminating redundant memory transfers [1,2] and by advancing or delaying the data copy operations [3]. Second, the pipelining technique builds on an enabling technique that deals with another important issue in accelerators: The accelerator's memory space is limited; computation that fits in the CPU's memory may exceed the accelerator's capacity.…”

Directive-Based Compilers for GPUs

“…It relies on pragmas, but it does not ease the programmer task as much as the Cray, CAPS or PGI compilers. Other experimental compilation tools like CGCM [16] and PAR4ALL [1] aim at automating the process of CPU-GPU communication and the detection of the pieces of code that can run in parallel. The work by Lee and Eigenmann [20] proposes OpenMPC, an API to facilitate translation of OpenMP programs to CUDA, and a compilation system to support it.…”

Beyond Do Loops: Data Transfer Generation with Convex Array Regions

“…4 As the write regions are empty for src, this corresponds to the loads. The SCALOPES project associated an asymmetric MP-SoC with cores dedicated to task scheduling, to a semi-automatic parallelization workow.…”

“…The second point has been addressed using simplied input from the programmer [13,27,19], or automatically [4,24,1,26] using compilers. This paper exposes how the array regions abstraction [11] can be used by a compiler to automatically compute memory transfers in presence of complex code patterns.…”