Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs

Coskun, Ayse K.; Rosing, Tajana; Whisnant, K.; Gross, Kenneth C.

doi:10.1109/tvlsi.2008.2000726

Cited by 137 publications

(106 citation statements)

References 32 publications

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“…We derive the thermal parameters and thickness of Si and Cu layers based on [13]. For benchmarking applications we have chosen several reallife applications which are run on the UltraSPARC T1 chip and the utilizations of the cores are noted as reported in [14]. From these utilization numbers we derived the power traces based on the average power values reported in [12].…”

Section: A Target System and Benchmark Applicationsmentioning

confidence: 99%

Neural network based on-chip thermal simulator

Kumar

Atienza

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract-With increasing power densities, runtime thermal management is becoming a necessity in today's systems, especially so for highly integrated Multi-Processor Systems-on-Chip (MPSoCs). In this paper, we propose a neural network (NN) based approach to implement an on-chip thermal simulator to aid such runtime management for MPSoCs. The proposed method combines the advantage of approximating the thermal properties of the chip as a linear system with the ease of fully parallel analog implementation of NNs. We perform a case study with the Niagara UltraSPARC T1 MPSoC for real-life applications, benchmarking our results with an accurate higher order Runge-Kutta (RK4) solver, that is employed in tools such as HotSpot. Within a few gate delays, the proposed NN design can simulate temperatures of the MPSoC 500 ms into the futurecorresponding to thousands of iterations of the RK4 solver, with a maximum error of 1-2 K.

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Section: A Target System and Benchmark Applicationsmentioning

confidence: 99%

Neural network based on-chip thermal simulator

Kumar

Atienza

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…However, thermallyaware design optimization techniques often target the worst-case or the average-case scenarios [92]. This may not be the usual case, as the thermal profile of a typical 3D MPSoC is mainly dependent on the workload conditions [100]. These workload conditions vary based on the processing and memory access activities [101], as well as the target processing domains.…”

Section: Temperature-aware Runtime Management For 3d Mpsocsmentioning

confidence: 99%

Temperature-Aware Design and Management for 3D Multi-Core Architectures

Sabry

Atienza

2014

FNT in Electronic Design Automation

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“…Suhendra et al [21] and Salamy [22] studied the problem of integrating task scheduling and memory partitioning among a heterogeneous multiprocessor system on chip with scratch pad memory. Other works [23,24,25,26,27,28,29,30] have studied issues related to task scheduling/allocation and memory partitioning on multiprocessor systems. Xue et al [31] proposed a dynamic resource partitioner for embedded applications in an MPSoC.…”

Section: Related Workmentioning

confidence: 99%

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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As the utilization of multiprocessors system-on-chip (MPSoC) is becoming ubiquitous, demands for effective allocation and scheduling techniques are needed more than ever to harness the power of MPSoCs. An MPSoC is a system consisting of multiple heterogeneous processing cores, memory hierarchies, and communication infrastructure to effectively overcome the power and clock constraints from single core architectures. MPSoCs provide the performance demanded by embedded applications especially real-time multimedia applications. This article presents effective techniques to partitioning the processing cores and memory budget in an MPSoC among multiple embedded applications possibly entering the system at different times. The proposed framework will study the structure of each application and predict the possible reduction in schedule time if more processors and/or memory budget are assigned to this application. The objective is to fairly divide the resources such that the schedule times for the applications are minimized. Results on different embedded applications workloads and under different system resources show the effectiveness of our techniques that were able to reduce the cycle count by 10.2 % on average compared to an effective technique in the literature.

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Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs

Cited by 137 publications

References 32 publications

Neural network based on-chip thermal simulator

Neural network based on-chip thermal simulator

Temperature-Aware Design and Management for 3D Multi-Core Architectures

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

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