State diagram design for implementing phase I of a Vector Symbol Decoder on an FPGA board

Intharasakul, R.; Tuntoolavest, Usana

doi:10.1109/iscit.2006.339990

2006 International Symposium on Communications and Information Technologies 2006

DOI: 10.1109/iscit.2006.339990

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State diagram design for implementing phase I of a Vector Symbol Decoder on an FPGA board

R. Intharasakul

Usana Tuntoolavest

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State diagram design for implementing phase I of a Vector Symbol Decoder on an FPGA board

Cited by 2 publications

References 6 publications

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