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Komuravelli, Rakesh; Sinclair, Matthew; Alsop, Johnathan; Huzaifa, Muhammad; Kotsifakou, Maria; Srivastava, Prakalp; Adve, Sarita V.; Adve, Vikram

doi:10.1145/2749469.2750374

Cited by 45 publications

(1 citation statement)

References 30 publications

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“…Gaussian-Emboss-Outline-MotionBlur GEMO Caltech 101 Gaussian-Emboss-MotionBlur-Outline GSME Caltech 101 Gaussian-Sharpen-MotionBlur-Emboss (pDMA)Komuravelli et al 2015]. PROMISE operates on INT8 data and requires a data layout transformation, both of which are handled by pDMA.…”

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confidence: 99%

ApproxHPVM: a portable compiler IR for accuracy-aware optimizations

Sharif

Srivastava

Huzaifa

et al. 2019

Proc. ACM Program. Lang.

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We propose ApproxHPVM, a compiler IR and system designed to enable accuracy-aware performance and energy tuning on heterogeneous systems with multiple compute units and approximation methods. ApproxH-PVM automatically translates end-to-end application-level quality metrics into accuracy requirements for individual operations. ApproxHPVM uses a hardware-agnostic accuracy-tuning phase to do this translation that provides greater portability across heterogeneous hardware platforms and enables future capabilities like accuracy-aware dynamic scheduling and design space exploration. ApproxHPVM incorporates three main components: (a) a compiler IR with hardware-agnostic approximation metrics, (b) a hardware-agnostic accuracy-tuning phase to identify error-tolerant computations, and (c) an accuracy-aware hardware scheduler that maps error-tolerant computations to approximate hardware components. As ApproxHPVM does not incorporate any hardware-specific knowledge as part of the IR, it can serve as a portable virtual ISA that can be shipped to all kinds of hardware platforms. We evaluate our framework on nine benchmarks from the deep learning domain and five image processing benchmarks. Our results show that our framework can offload chunks of approximable computations to special-purpose accelerators that provide significant gains in performance and energy, while staying within user-specified application-level quality metrics with high probability. Across the 14 benchmarks, we observe from 1-9x performance speedups and 1.1-11.3x energy reduction for very small reductions in accuracy. CCS Concepts: • Software and its engineering → Compilers.

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confidence: 99%

ApproxHPVM: a portable compiler IR for accuracy-aware optimizations

Sharif

Srivastava

Huzaifa

et al. 2019

Proc. ACM Program. Lang.

Self Cite

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A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity

Khairy

Wassal

Zahran

2019

Journal of Parallel and Distributed Computing

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Automatic management of Software Programmable Memories in Many‐core Architectures

Shrivastava

Dutt

Cai

et al. 2016

IET Computers & Digital Techniques

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Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilized in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of manycore architectures. This article presents an overview of the state of the art in SPM management techniques in manycore processors, summarizes some recent research on SPM-based systems, and outlines future research directions in this field.

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Cited by 45 publications

References 30 publications

ApproxHPVM: a portable compiler IR for accuracy-aware optimizations

ApproxHPVM: a portable compiler IR for accuracy-aware optimizations

A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity

Automatic management of Software Programmable Memories in Many‐core Architectures

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