2016
DOI: 10.1109/jproc.2016.2574939
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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

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Cited by 111 publications
(58 citation statements)
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“…The computer architecture, where nonvolatile elements are located on a chip with CMOS devices, is traditionally called logic-in-memory, although as of yet no information is processed in nonvolatile elements. Power-efficient MRAMbased logic-in-memory concepts have already been demonstrated [71]. They include field-programmable gate arrays and ternary content addressable memory, as well as other variants.…”
Section: Nonvolatile Computingmentioning
confidence: 99%
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“…The computer architecture, where nonvolatile elements are located on a chip with CMOS devices, is traditionally called logic-in-memory, although as of yet no information is processed in nonvolatile elements. Power-efficient MRAMbased logic-in-memory concepts have already been demonstrated [71]. They include field-programmable gate arrays and ternary content addressable memory, as well as other variants.…”
Section: Nonvolatile Computingmentioning
confidence: 99%
“…These CMOS/spintronic hybrid solutions are already competitive in comparison to the conventional CMOS technology with respect to power consumption and speed. The introduction of nonvolatility in circuits helps cutting the power consumption by 50%, with outstanding 90% reduction in specific circuits [71].…”
Section: Nonvolatile Computingmentioning
confidence: 99%
“…MTJ with a high TMR can guarantee easy access to peripheral CMOS blocks, e.g., sensing and control circuits [28][29][30][31][32]. The real value of TMR (TMR(V)) can be adjusted by changing zero bias (TMR(0)) and V h (half of TMR (0)):…”
Section: Stt-mtjmentioning
confidence: 99%
“…High-density STT-MRAM arrays with 4Gbit capacities have been already demonstrated [3]. The availability of high-capacity non-volatile memory positioned close to highperformance CMOS circuits opens a new horizon in exploring conceptually new logic-in-memory [4] and computing-in-memory architectures for future artificial intelligence and cognitive computing.…”
mentioning
confidence: 99%
“…In addition, rapidly increasing critical currents for switching STT-MRAM at 5ns and faster reduce the endurance to that of the flash memory. The development of an electrically addressable non-volatile memory combining high speed (sub-ns operation) and high endurance is essential for replacing SRAM) in high-level caches of hierarchical multi-level processor memory structures with a non-volatile memory [4]. The spin-orbit torque MRAM (SOT-MRAM) with perpendicular magnetization combines non-volatility, high speed, and high endurance, which makes it suitable for applications in caches [5].…”
mentioning
confidence: 99%