Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process

Zhang, W.; Zhao, Chun; Man, Ka Lok; Jeong, Taikyeong; Seon, Jong-Kug; Lee, Y.

doi:10.1109/isocc.2011.6138771

Cited by 2 publications

(1 citation statement)

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“…Standard cells are not only employed for logic synthesis and physical design in digital implementation flow but are also adopted in mixed-signal process for different applications considering performance, cost and power consumption [8]. The insufficient resource of pins in standard cells is dominated the insertion rate of vial [9].…”

Section: Introductionmentioning

confidence: 99%

Configurable redundant via-aware standard cell design considering multi-via mechanism

Kan

Hong

Chen

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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�ell designed redundant via-aware standard ceHs (SCs) can mcrease the redundant vial insertion rate in ceH-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low vial insertion rate in nanometer regimes, but also demonstrates an efficient automatie layout optimizer for designing standard ceHs. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant vial insertion rate by a total of 26.3%. KeywordsDesign for manufacturability (DFM), layout, redundant via, standard ceH (SC)

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Section: Introductionmentioning

confidence: 99%