SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA

Kumar, Keshav; NP, Stenin; Pandey, Pushpanjali; Pandey, Bishwajeet; Gohel, Hardik

doi:10.1109/csnt60213.2024.10546070

2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT) 2024

DOI: 10.1109/csnt60213.2024.10546070

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SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA

Keshav Kumar,

Stenin NP,

Pushpanjali Pandey

et al.

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SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA

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References 16 publications

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