SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA

Abstract

In

Power and Time Delay Analysis of Simple Comparator Implemented On Different Type of FPGA

“…The same is done by some scientist, virtually using Xilinx, i.e. observing the timing constraint [8] and power [9] for different projects [11]. In contrary to this, we has compared level of power consumed and delays encountered by the simple comparator algorithm for different platforms of FPGA.…”

Design of Energy Efficient Sinusoidal PWM Waveform Generator on FPGA

“…In this reference [2] researcher have designed an energy efficient Multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Another researcher have performed power dissipation analysis of DES algorithm, implemented on a 28nm FPGA [3]. Some researcher have used thermal aware approach in an encoder design and also testing thermal stability by working on different ambient temperatures [4].…”

Implementation of Temperature Sensor for LVCMOS25 Using Virtex6 FPGA

“…In future, temperature sensor can attain even lower power than this using other IO standards like SSTL, HSTL, LVDCI, HSUL, Mobile DDR, PCI, GTL etc. [5]. Capacitance scaling is used here.…”