SSA-Based Register Allocation with PBQP

Buchwald, Sebastian; Zwinkau, Andreas; Bersch, Thomas

doi:10.1007/978-3-642-19861-8_4

Cited by 5 publications

(3 citation statements)

References 15 publications

(25 reference statements)

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“…The practical applicability of the developed methods and algorithms for automating code generation for DSL compilers for specialized processors is confirmed by the experimental evaluation of the created JC compiler on a set of applications. NOLTIS [16], PBQP [17], CP [18] SAT [19], ILP [20], CP [21] Graph coloring [22], puzzle method [23], ILP [24], PBQP [25] ILP [26] ILP [27], CP [28] ILP [29]…”

Section: Discussionmentioning

confidence: 99%

Development of DSL Compilers for Specialized Processors

Sovetov

2021

Program Comput Soft

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Modern computer systems often include specialized processors that are programmed in domainspecific languages. The compiler-in-the-loop technology, which assumes the joint development of the dedicated processor and compiler, gains in popularity. In this case, the conventional tools (such as GCC and LLVM) are insufficient for the rapid development of optimizing compilers that generate the target code for irregular architectures and static parallelism of operations. In this paper, it is proposed to use methods for solving NP-complete problems for the implementation of machine-dependent compilation phases. These phases are based on the reduction to the SMT problem, which makes it possible to get rid of heuristic and approximate approaches that require complicated software implementation. In particular, it is proposed to implement the synthesis of machine-dependent optimization rules, instruction selection, instruction scheduling, and register allocation using an SMT solver. Practical applications of the developed methods and algorithms are illustrated by the example of a compiler for a specialized processor with an instruction set that accelerates the implementation of lightweight cryptography algorithms on the Internet of Things. The results of compilation and simulation of eight cryptographic primitives for three variants of the specialized processor (CISC-like, VLIW-like and a variant with delayed load instruction) show the practical usefulness of the proposed approach.

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Section: Discussionmentioning

confidence: 99%

Development of DSL Compilers for Specialized Processors

Sovetov

2021

Program Comput Soft

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“…Планирование команд Распределение регистров NOLTIS [16], PBQP [17], CP [18] SAT [19], ЦЛП [20], CP [21] Раскраска графа [22], метод головоломок [23], ЦЛП [24], PBQP [25] ЦЛП [26] ЦЛП [27], CP [28] ЦЛП [29]…”

Section: выбор командunclassified

Accelerating the Development of DSL Compilers for Specialized Processors

Советов¹

2020

Proceedings of ISP RAS

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Specialized processors programmable in domain-specific languages are increasingly used in modern computing systems. The compiler-in-the-loop approach, based on the joint development of a specialized processor and a compiler, is gaining popularity. At the same time, the traditional tools, like GCC and LLVM, are insufficient for the agile development of optimizing compilers that generate target code of an exotic, irregular architecture with static parallelism of operations. The article proposes methods from the field of program synthesis for the implementation of machine-dependent compilation phases. The phases are based on a reduction to SMT problem which allows to get rid of heuristic and approximate approaches, that requires complex software implementation of a compiler. In particular, a synthesis of machine-dependent optimization rules, instruction selection and instruction scheduling combined with register allocation are implemented with help of SMT solver. Practical applications of the developed methods and algorithms are illustrated by the example of a compiler for a specialized processor with an instruction set that accelerates the implementation of lightweight cryptography algorithms in the Internet of Things. The results of compilation and simulation of 8 cryptographic primitives for 3 variants of specialized processor (CISC-like, VLIW-like and a variant with delayed load instruction) show the vitality of the proposed approach.

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“…For them, handling the irregularities well is somewhat easier, but still challenging; ILP and PBQP are NP-hard problems, which can be problematic for the runtime of the allocators. There also are decoupled approaches based on ILP [1] and PBQP [6]. A recent approach based on graph-structure theory combines the elegance of graph-coloring approaches with the ability to easily handle any irregularities and aliasing [17].…”

Section: Introductionmentioning

confidence: 99%

Bytewise Register Allocation

Krause

2015

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems

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Traditionally, variables have been considered as atoms by register allocation: Each variable was to be placed in one register, or spilt (placed in main memory) or rematerialized (recalculated as needed). Some lexibility arose from what would be considered a register: Register aliasing allowed to treat a register meant to hold a 16-bit variable as two registers that could hold an 8-bit variable each. We allow for far more lexibility in register allocation: We decide on the storage of variables bytewise, i. e. we decide for each individual byte in a variable whether to store it in memory or a register, and consider any byte of any register as a possible storage location.We implemented a backend for the STM8 architecture (STMicroelectronics' current 8-bit architecture) in the Ccompiler sdcc, and experimentally evaluate the beneits of bytewise register allocation. The results show that bytewise register allocation can result in substantial improvements in the generated code. Optimizing for code size we obtained 27.2%, 13.2% and 9.2% reductions in code size in the Whetstone, Dhrystone and Coremark benchmarks, respectively, when using bytewise allocation and spilling compared to conventional allocation.

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SSA-Based Register Allocation with PBQP

Cited by 5 publications

References 15 publications

Development of DSL Compilers for Specialized Processors

Development of DSL Compilers for Specialized Processors

Accelerating the Development of DSL Compilers for Specialized Processors

Bytewise Register Allocation

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