SRC physical design top ten problem

Parkhurst, Jeff; Sherwani, Naveed A.; Maturi, Sury; Ahrams, Dana; Chiprout, Eli

doi:10.1145/299996.300022

Cited by 15 publications

(1 citation statement)

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“…Since more and more circuit components can be integrated on a single chip with the limitation of storage space and packaging process, the VLSI design approach faces new challenges. Among them, routing is one of the top ten problems that the current physical design needs to solve urgently [25]. In terms of chip size and capacity, the routing problem requires a circuit chip scale of tens of thousands of large modules and millions of small modules, and requires this work to be completed within a reasonable time.…”

Section: Routing Problems In Vlsimentioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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Routing is a complex and critical stage in the physical design of Very Large Scale Integration (VLSI), minimizing interconnect length and delay to optimize overall chip performance. With the rapid development of modern technology, VLSI routing faces enormous challenges such as large delay, high congestion, and high-power consumption. As a rising optimization method, Swarm Intelligence (SI) inspired from collective intelligence behaviors through cooperation or interaction with the environment provides effectiveness and robustness for solving NP-hard problems. Many researchers have consequently used SI techniques to solve routing-related problems in VLSI. This paper reviews the application of several SI techniques to the VLSI routing filed. Firstly, five commonly used SI techniques and related models, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing. Then an overview of the current state of this field is given according to the above categories, and the survey offers informative discussions from five aspects: 1) Steiner minimum tree construction; 2) wirelength-driven routing; 3) obstacle-avoiding routing; 4) timing-driven routing; 5) power-driven routing. Finally, under three new technology models: X-architecture, multiple dynamic supply voltage and via-pillar, the future development trends are pointed as follows: 1) suggesting suitable SI techniques to specific routing problems for advanced technology models; 2) exploring new and available SI techniques that have not yet been applied to VLSI routing.

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Section: Routing Problems In Vlsimentioning

confidence: 99%