SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Cho, Keonhee; Choi, Heekyung; Jung, Insoo; Oh, Jisang; Oh, Tae Woo; Kim, Kiryong; Kim, Giseok; Choi, Tae-Yong; Sim, Chang-Soo; Song, Taejoong; Jung, Seong‐Ook

doi:10.23919/vlsicircuits52068.2021.9492505

2021 Symposium on VLSI Circuits 2021

DOI: 10.23919/vlsicircuits52068.2021.9492505

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SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Keonhee Cho

Heekyung Choi

Insoo Jung

et al.

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15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

Yeo,

Cho,

Kim

et al. 2024

2024 IEEE International Solid-State Circuits Conference (ISSCC)

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15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

Yeo,

Cho,

Kim

et al. 2024

2024 IEEE International Solid-State Circuits Conference (ISSCC)

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SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Cited by 1 publication

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15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

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