SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy

SIERRA—Simulation environment for memory redundancy algorithms

“…The code in the example assumes that both spare rows and columns are available for repairing faulty cells. It describes a simple repair strategy that first tries to repair detected faulty cells using spare rows (line [31][32][33][34]. Once all the spare rows have been consumed, it tries to repair the memory array using spare columns (line [22][23][24][25][26][27][28][29][30].…”

“…Keywords are also reserved to specify MRA actions. Possible actions are: interrupt the test and repair process, skip to repair the current faulty cell, repair the faulty cell with a specific spare resource, reset the test and repair process, or repair more than one faulty cell at a time, as required by most state-of-the-art MRAs [31,32]. Furthermore, some MRAs require the ability to undo previously executed spare allocations and re-execute the fault detection sequence.…”