Spur reduction in bang-bang PLLs using programmable bit-stream

Bashiri, Samira; Aouini, Sadok; Plett, C.; Ben-Hamida, Naim

doi:10.1049/el.2011.2226

Cited by 2 publications

(3 citation statements)

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“…The adaptive selection can alternatively be implemented in pure analogue hardware, although the use of the microprocessor [3] controlled digital offers more flexibility. The selection policy depends mainly on the center frequency.…”

Section: Design Of the Multiple Rate Pllmentioning

confidence: 99%

Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

Liu¹,

Qian²,

Huang

et al. 2015

Proceedings of the 2015 International Power, Electronics and Materials Engineering Conference

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This paper studies the frequency synthesis for precision time protocol clock generation circuit, and more particularly focused on a multi-rate phase locked loop structure for generating an output signal at a desired frequency with reduced jitter towards the magnitude of femtosecond. We proposed a unique structured model that makes use of a multiple rate digital filter to match the noise spectrum characteristics of both input digital controlled oscillator reference and output voltage controlled oscillator respectively. The simulation for two rate case is carried out. This concept can be extended to more than two rates to match with additional noise sources' spectrum from the other devices such as fractional divider, etc.

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Section: Design Of the Multiple Rate Pllmentioning

confidence: 99%

Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

Liu¹,

Qian²,

Huang

et al. 2015

Proceedings of the 2015 International Power, Electronics and Materials Engineering Conference

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“…Using the bit stream helps to reduce the spurious tones by dithering the reference and breaking the cyclic patterns in the control signal. This work is published in IEEE Electronics Letters Journal, [2].…”

Section: Motivation and Contributionsmentioning

confidence: 99%

“…The system level technique that was used to improve the performance of the BBPLL, described in Section 1 of Chapter 4, which employs a software based random bit-stream for reference to dither the input of the BBPLL is published in IEEE Electronics Letters Journal, [2].…”

Section: Contributionsmentioning

confidence: 99%

Design, Analysis and Modeling of the Effect of the Phase Detector in Digital Phase-Locked Loops

Amid¹

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ii Abstract The limitations and the effect of the performance of the binary phase detector on the overall performance of the digital phase-locked loop is the main focus of the research presented in this proposal. In the first part of the research, the gain limitation of the binary phase detector on the performance of the digital Bang-Bang phase-locked loop is investigated. Then to validate the concept that is explained and to improve the performance of the digital loop under the gain limitation, two schemes are explored and explained. In one scheme a random bit-stream which is noise-shaped using a software defined Σ∆ modulator is used to dither the reference and improve the performance and in the second scheme a Time-Amplifier is used to improve the digital loop performance by preventing the phase detector from operating in metastable region.The second part of the research focuses on a novel multi-bit phase detector for high-speed applications where high-resolution performance is needed and the jitter budget is stringent. In this design a Transmission Delay Line is used to generate the delayed versions of the input clock. The performance of this phase detector is analyzed in detail using stochastic analysis.In the second multi-bit phase detector a search algorithm is used to find i the closest delayed reference to the feedback clock. This scheme provides superior performance compared to the first scheme as its performance is not affected by the mismatch of the binary phase detectors used in the first scheme. The performance of the two design are compared and example of the performance in the loop is provided.ii

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Spur reduction in bang-bang PLLs using programmable bit-stream

Cited by 2 publications

References 1 publication

Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

Design Phase Locked Loop Accuracy towards Femtosecond Magnitude

Design, Analysis and Modeling of the Effect of the Phase Detector in Digital Phase-Locked Loops

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