SPRAT: Runtime processor selection for energy-aware computing

Takizawa, Hiroyuki; Sato, Koya; Kobayashi, Hiroaki

doi:10.1109/clustr.2008.4663799

Cited by 28 publications

(23 citation statements)

References 11 publications

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“…The paper also demonstrates the utility of the framework by employing the optimizations of bus encoding and repeater sizing/spacing. Takizawa et al [20] propose a programming framework called SPART, short for stream programming with runtime auto-tuning, that dynamically selects the best available processor for execution of a given task on a hybrid computing system of CPU and GPU so as to improve the energy efficiency.…”

Section: Related Workmentioning

confidence: 99%

On the energy efficiency of graphics processing units for scientific computing

Huang

Xiao

Feng

2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

155

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The graphics processing unit (GPU) has emerged as a computational accelerator that dramatically reduces the time to discovery in high-end computing (HEC). However, while today's state-of-the-art GPU can easily reduce the execution time of a parallel code by many orders of magnitude, it arguably comes at the expense of significant power and energy consumption. For example, the NVIDIA GTX 280 video card is rated at 236 watts, which is as much as the rest of a compute node, thus requiring a 500-W power supply. As a consequence, the GPU has been viewed as a "nongreen" computing solution.This paper seeks to characterize, and perhaps debunk, the notion of a "power-hungry GPU" via an empirical study of the performance, power, and energy characteristics of GPUs for scientific computing. Specifically, we take an important biological code that runs in a traditional CPU environment and transform and map it to a hybrid CPU+GPU environment. The end result is that our hybrid CPU+GPU environment, hereafter referred to simply as GPU environment, delivers an energy-delay product that is multiple orders of magnitude better than a traditional CPU environment, whether unicore or multicore.

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Section: Related Workmentioning

confidence: 99%

On the energy efficiency of graphics processing units for scientific computing

Huang

Xiao

Feng

2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

155

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“…Ramani et al proposed a modular architectural power estimation framework that would help GPU designers with early power efficiency exploration [8]. Takizawa et al proposed the SPRAT runtime environment that dynamically selects CPU or GPU as an appropriate processor, so as to improve the overall energy efficiency [9]. Xiaohan et al presented a scheme to statistically analyze and model the power computing of a GPU by exploiting the intrinsic coupling among power consumption, runtime performance, and dynamic workloads of GPUs [10].…”

Section: Related Workmentioning

confidence: 99%

A Study on Improving Power-Consumption Performance Ratio in GPGPU Computing

Matsumoto

Yamaguchi

Sakai³

2011

2011 Second International Conference on Networking and Computing

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Increased power consumption of computer has become an important issue in computer systems. Especially in high performance computing, its huge consumption is a serious issue. In this paper, we analyze relationship between performance and power consumption on GPGPU computing, and present a method of improving power-consumption performance ratio. First, we introduce an approach to measuring power consumption of a GPU. Second, we explore performance and power consumption, and discuss a way to improve its performance without substantial power consumption increase. Our experimental results demonstrate that memory access coalescing, utilizing shared memory, and making use of a large quantity of threads improve power-consumption performance ratio.

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“…However, this body of work is very abstract and focused purely on asymptotics, making these models difficult to operationalize, in our view. Lastly, there is a considerable body of work from the embedded hardware/software community, emphasizing analysis suitable for compilerand run-time systems [15,33,53]. However, this work necessarily focuses on specific concrete code and architecture implementations, and therefore do not explicitly illuminate constraints due to fundamental algorithmic and physical limits.…”

Section: Background and Related Workmentioning

confidence: 99%

A Theoretical Framework for Algorithm-Architecture Co-design

Czechowski

Vuduc

2013

2013 IEEE 27th International Symposium on Parallel and Distributed Processing

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Abstract-We consider the problem of how to enable computer architects and algorithm designers to reason directly and analytically about the relationship between high-level architectural features and algorithm characteristics. We propose a modeling framework designed to help understand the long-term and high-level impacts of algorithmic and technology trends. This model connects abstract communication complexity analysis-with respect to both the inter-core and inter-processor networks and the memory hierarchy-with current technology proposals and projections. We illustrate how one might use the framework by instantiating a particular model for a class of architectures and sample algorithms (threedimensional fast Fourier transforms, matrix multiply, and three-dimensional stencil). Then, as a suggestive demonstration, we analyze a number of what-if scenarios within the model in light of these trends to suggest broader statements and alternative futures for power-constrained architectures and algorithms.

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SPRAT: Runtime processor selection for energy-aware computing

Cited by 28 publications

References 11 publications

On the energy efficiency of graphics processing units for scientific computing

On the energy efficiency of graphics processing units for scientific computing

A Study on Improving Power-Consumption Performance Ratio in GPGPU Computing

A Theoretical Framework for Algorithm-Architecture Co-design

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