Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating Points

Abstract

The paper is focused on local spot defect diagnosis in nonlinear analog integrated circuits. The defects are simulated by finite resistors, high in the case of open and low in the case of short. A diagnostic method that allows detecting, locating, and estimating the value of the defect is developed. The method employs the simulation before test approach leading to a fault dictionary and brings a procedure for locating the defect and estimating its value, on the basis of some quantities measured during the diagnostic test. Because the nonlinear circuit under test may have multiple operating points, even if the fault-free circuit has a unique solution, building the fault dictionary requires a special approach. It is based on some families of characteristics, expressing the resistances that simulate the defects in terms of several voltages, taking into account the deviations of the fault-free parameters within their tolerance ranges. To illustrate the proposed approach two numerical examples are given.

Analog Circuit Specification Testing by Means of Walsh–Hadamard Transform and Multiple Regression Supported by Evolutionary Computations

“…The 100 patterns for the CUT discrete elements parameters dispersed randomly in their tolerance regions δ DEV = ± 5% (set I) and for eight Table 4 CUT performance parameters estimation errors and their standard deviations assumed special cases with the one selected element value shifted from the nominal point and randomly determined other ones (set II) were tested during this experiment. The filter circuit performance parameters were calculated basing on the regression models found evolutionarily (22)(23)(24)(25)(26)(27)(28)(29)(30)(31). Finally, identically as in [31], the CUT pattern is classified into the good ones if all the tested performance parameters do not exceed the allowed tolerance absolute deviation ± | p i | from the nominal level specified and to the faulty ones otherwise ( Table 5).…”

“…The parametric local and global faults of transistors of CMOS structure based on homotopy idea and the simplicial algorithm were proposed in [28]. Catastrophic fault detection method dedicated to nonlinear circuits was described in [29]; however, work [30] presents the technique dedicated to the diagnosis of spot defects. In works [24,26,27], the approaches based on sensitivity analysis for faulty element identification, test measurements ambiguity sets determination and optimal frequency of testing signal selection, respectively, may be found.…”

Diagnosis of Soft Spot Short Defects in Analog Circuits Considering the Thermal Behaviour of the Chip

“…If a faulty parameter drifts from its tolerance range, but does not lead to some topological changes, the fault is said to be the soft or parametric one. Most physical failures (80-90)% in integrated circuits are opens and shorts [9][10]21]. In both CMOS and BJT circuits (70-80)% of failures are shorts and (10-20)% opens.…”

“…In consequence, the circuit parameters vary. In the reference [21] a method of spot defect diagnosing analogue circuits based on parametric characteristic tracing is proposed. The approach enables to test the circuits with multiple operating points but fails to consider the thermal effects.…”

Multiple soft fault diagnosis of DC analog CMOS circuits designed in nanometer technology

“…If a fault is open circuit or short circuit, it is called hard or catastrophic. In integrated circuits physical imperfections, such as near-opens or near-shorts may occur as spot defects [7,10,21,22]. The methods dedicated to soft fault diagnosis usually exploit the simulation after test approach, where circuit simulations take place after any testing.…”