Splash 2

Arnold, Jeffrey M.; Buell, Duncan A.; Davis, Elaine G.

doi:10.1145/140901.141896

Cited by 130 publications

(53 citation statements)

References 3 publications

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“…We ran several standard Splash2 [12] applications using the Hood scheduler [13] with the ABP and new work-stealing algorithms. Our results, presented in Section 3, show that the new algorithm performs as well as ABP, that is, the added dynamic-memory feature does not slow the applications down.…”

Section: Performance Analysismentioning

confidence: 99%

“…Our preliminary results include tests running several standard Splash2 [12] applications using the Hood Library [13] on a 16 node Sun Enterprise TM 6500, an SMP machine formed from 8 boards of two 400MHz UltraSparc processors, connected by a crossbar UPA switch, and running a Solaris TM 9 operating system. Our benchmarks used the work-stealing algorithms as the load balancing mechanism in Hood.…”

Section: Performancementioning

confidence: 99%

“…We present our results running the Barnes Hut and MergeSort Splash2 [12] applications. Each application was compiled with the minimal ABP deque size needed for a stand-alone run with the biggest input tested.…”

Section: Performancementioning

confidence: 99%

“…none of the deques overflowed. Figure 6 shows the results of running the Barnes Hut [12] application (on the largest input) in a multiprogrammed fashion by running multiple instances of Hood in parallel. The graph shows the completion rate of both algorithms as a function of the multiprogramming level (i.e.…”

Section: Performancementioning

confidence: 99%

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Dynamic Memory ABP Work-Stealing

Hendler

Lev

Shavit

2004

Lecture Notes in Computer Science

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Abstract. The non-blocking work-stealing algorithm of Arora, Blumofe, and Plaxton (hencheforth ABP work-stealing) is on its way to becoming the multiprocessor load balancing technology of choice in both Industry and Academia. This highly efficient scheme is based on a collection of array-based deques with low cost synchronization among local and stealing processes. Unfortunately, the algorithm's synchronization protocol is strongly based on the use of fixed size arrays, which are prone to overflows, especially in the multiprogrammed environments which they are designed for. This is a significant drawback since, apart from memory inefficiency, it means users must tailor the deque size to accommodate the effects of the hard-to-predict level of multiprogramming, and add expensive blocking overflow-management mechanisms. This paper presents the first dynamic memory work-stealing algorithm. It is based on a novel way of building non-blocking dynamic memory ABP deques by detecting synchronization conflicts based on "pointercrossing" rather than "gaps between indexes" as in the original ABP algorithm. As we show, the new algorithm dramatically increases robustness and memory efficiency, while causing applications no observable performance penalty. We therefore believe it can replace array-based ABP work-queues, eliminating the need to add application specific overflow mechanisms.

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Section: Performance Analysismentioning

confidence: 99%

Section: Performancementioning

confidence: 99%

Section: Performancementioning

confidence: 99%

Section: Performancementioning

confidence: 99%

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Dynamic Memory ABP Work-Stealing

Hendler

Lev

Shavit

2004

Lecture Notes in Computer Science

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“…Besides our PAMs, which were built rst at IN-RIA in 1987 [4], then at DEC-PRL, other successful implementations of recongurable systems have been reported, in particular at the universi- ties of Edinburgh [5] and Zurich [6], and at the Supercomputer Research Center in Maryland [7]. The ENABLE machine is a system, built from FPGAs and SRAM, specically constructed at the university of Mannheim [8] for solving the TRT problem of section 3.2.…”

Section: Programmable Active Memoriesmentioning

confidence: 99%

Real-time high-energy physics applications on DECPeRLe-1 programmable active memory

Moll

Vuillemin

Boucard³

et al. 1996

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. The future Large Hadron Collider (LHC) to be built at CERN 1 , by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST 2 (RD-11) group and DEC-PRL PAM 3 team. We present implementations of the four foremost LHC algorithms on DECPeRLe-1 [1]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based machine built for just one of the algorithms [2]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

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Reconfigurable Computing

Chung-Kuan¹,

Kahng²,

Leong³

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric to two massively multi-core hardware platforms. The TFIDF classifier is used to detect web attacks in HTTP data. In our parallel hardware approaches, we design streaming, real time classifiers by simplifying the sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. Parallel implementations on the Tilera 64-core System on Chip and the Xilinx Virtex 5-LX FPGA are presented. For the Tilera, we employ a reduced state machine to recognize dictionary terms without requiring explicit tokenization, and achieve throughput of 37 MB/s at a slightly reduced accuracy. For the FPGA, we have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires 0.2% of the memory used by the original algorithm. At 166 MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.

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Splash 2

Cited by 130 publications

References 3 publications

Dynamic Memory ABP Work-Stealing

Dynamic Memory ABP Work-Stealing

Real-time high-energy physics applications on DECPeRLe-1 programmable active memory

Reconfigurable Computing

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