Spintronics for Energy- Efficient Computing: An Overview and Outlook

Guo, Zongxia; Yin, Jialiang; Bai, Yanling; Zhu, Daoqian; Shi, Kewen; Gefei, Wang; Cao, Kaihua; Zhao, Weisheng

doi:10.1109/jproc.2021.3084997

Cited by 140 publications

(65 citation statements)

References 164 publications

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“…STT-MRAM are believed to be more suitable to embedded memory applications for industrial-grade MCUs, autonomous vehicles and various IoT devices [50]. Using its high-speed nature, STT-MRAM has been considered as an alternative of SRAM applications [51] as well as L3/L4 cache replacement, which requires high performance in terms of density, write efficiency, bandwidth, and endurance [52].…”

Section: Many Other Companies Are Currently Developingmentioning

confidence: 99%

“…Emerging writing mechanisms of MRAM cells, such as SOT and VCMA, have been intensively studied for the next generation of MRAM [26,50,53,54]. Waferscale SOT-MRAMs compatible with CMOS technologies have been demonstrated [55], together with fast switching demonstration (less than 400 ps) in a perpendicularly magnetised SOT-MRAM cell [56], show highspeed switching, as well as improved endurance for both standalone-memory and processing-in-memory (PIM) applications [57].…”

Section: Many Other Companies Are Currently Developingmentioning

confidence: 99%

“…Spintronics is another promising approach that can advance the state-of-the-art in multiple paradigms of com-puting. Spintronic memory and logic circuits are expected to open a novel route to manipulate information more efficiently and their prototypes have been actively proposed [26,50,53,54]. In the coming decade, we predict an increased dominance of hybrid CMOS-spintronic computing architectures based on MRAM techniques such as STT, SOT and VCMA.…”

Section: Outlook and Conclusionmentioning

confidence: 99%

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Memristive, Spintronic, and 2D-Materials-Based Devices to Improve and Complement Computing Hardware

Joksas,

AlMutairi,

Lee

et al. 2022

Preprint

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In a data-driven economy, virtually all industries benefit from advances in information technology-powerful computing systems are critically important for rapid technological progress. However, this progress might be at risk of slowing down if we do not address the discrepancy between our current computing power demands and what the existing technologies can offer. Key limitations to improving the energy efficiency are the excessive growth of data transfer costs associated with the von Neumann architecture and the fundamental limits of complementary metal-oxide-semiconductor (CMOS) technologies, such as transistors. In this perspective article, we discuss three technologies that will likely play an essential role in future computing systems: memristive electronics, spintronics, and electronics based on 2D materials. We present some representative applications for each and speculate how these could fit within future digital, quantum and neuromorphic systems.

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Section: Many Other Companies Are Currently Developingmentioning

confidence: 99%

Section: Many Other Companies Are Currently Developingmentioning

confidence: 99%

Section: Outlook and Conclusionmentioning

confidence: 99%

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Memristive, Spintronic, and 2D-Materials-Based Devices to Improve and Complement Computing Hardware

Joksas,

AlMutairi,

Lee

et al. 2022

Preprint

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“…On-chip learning is known to provide several advantages for edge devices in terms of data security and the like [6,7]. This makes the domain-wall synapse device an important device in the context of the ongoing research on spintronics-based neuromorphic computing [19][20][21][22][23][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network

Desai¹,

Kaushik²,

Sharda³

et al. 2022

Neuromorph. Comput. Eng.

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Domain-wall-synapse-based crossbar arrays have been shown to be very efficient, in terms of speed and energy consumption, while implementing fully connected neural network (FCNN) algorithms for simple data-classification tasks, both in inference and on-chip-learning modes. But for more complex and realistic data-classification tasks, convolutional neural networks (CNN) need to be trained through such crossbar arrays. In this paper, we carry out device-circuit-system co-design and co-simulation of on-chip learning of a CNN using a domain-wall-synapse-based crossbar array. For this purpose, we use a combination of micromagnetic-physics-based synapse-device modeling, SPICE simulation of a crossbar-array circuit using such synapse devices, and system-level-coding using a high-level language. In our design, each synaptic weight of the convolutional kernel is considered to be of 15 bits; one domain-wall-synapse crossbar array is dedicated to the 5 least significant bits (LSBs), and two crossbar arrays are dedicated to the other bits. The crossbar arrays accelerate the matrix vector multiplication (MVM) operation involved in the forward computation of the CNN. The synaptic weights of the LSB crossbar are updated after forward computation on every training sample, while the weights of the other crossbars are updated after forward computation on 10 samples, to achieve on-chip learning. We report high classification-accuracy numbers for different machine-learning data sets using our method. We also carry out a study of how the classification accuracy of our designed CNN is affected by device-to-device variations, cycle-to-cycle variations, bit precision of the synaptic weights, and the frequency of weight updates.

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“…In recent years, many non-volatile memories (NVMs), such as resistive random-access memory (ReRAM) [9][10][11], phase change memory (PCM) [12,13], and magnetoresistive random-access memory (MRAM) [14,15], provide PIM with a new research platform. Among all emerging NVM technologies, MRAM has emerged as a promising high-performance candidate for the main memory due to its non-volatility, superior endurance, zero standby leakage, compatibility with the CMOS fabrication process and high integration density [16].…”

Section: Introductionmentioning

confidence: 99%

NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration

Zhao,

Yang,

et al. 2022

Preprint

Self Cite

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The performance and efficiency of running large-scale datasets on traditional computing systems exhibit critical bottlenecks due to the existing power wall and memory wall problems. To resolve those problems, processing-in-memory (PIM) architectures are developed to bring computation logic in or near memory to alleviate the bandwidth limitations during data transmission. NAND-like spintronics memory (NAND-SPIN) is one kind of promising magnetoresistive random-access memory (MRAM) with low write energy and high integration density, and it can be employed to perform efficient in-memory computation operations. In this work, we propose a NAND-SPIN-based PIM architecture for efficient convolutional neural network (CNN) acceleration. A straightforward data mapping scheme is exploited to improve the parallelism while reducing data movements. Benefiting from the excellent characteristics of NAND-SPIN and in-memory processing architecture, experimental results show that the proposed approach can achieve ∼2.6× speedup and ∼1.4× improvement in energy efficiency over state-of-the-art PIM solutions.

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Spintronics for Energy- Efficient Computing: An Overview and Outlook

Cited by 140 publications

References 164 publications

Memristive, Spintronic, and 2D-Materials-Based Devices to Improve and Complement Computing Hardware

Memristive, Spintronic, and 2D-Materials-Based Devices to Improve and Complement Computing Hardware

On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network

NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration

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