SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

Abstract

The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker-Spiking Neural Network architecture-is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.Index Terms-Asynchronous interconnect, chip multiprocessor, energy efficiency, globally asynchronous locally synchronous (GALS), network-on-chip, neuromorphic hardware, real-time simulation, spiking neural networks (SNNs).

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip

“…The compiled code is then downloaded to ITCM while any data structures, including LUTs for exponential function, that are used while application is running, are stored in DTCM. See [19] for a more detailed review of the architecture and software; Also see [20] for comparison to other neuromorphic systems.…”

Event-based neural computing on an autonomous mobile platform

“…SpiNNaker 1) Hardware: SpiNNaker [8] is a digital multi-core multichip architecture oriented to the simulation of large neural networks in real-time. Each SpiNNaker chip (octagons in Figure 2) is equipped with 1Gbit SDRAM, storing synaptic information and accessible by parallel DMA requests (for an aggregate bandwidth of 900 MBytes/s [18]), by 18 programmable ARM968 cores embedded in a configurable packet-switched asynchronous fabric, based on an on-chip Multicast (MC) Router capable of handling one-tomany communication of spikes (packets) very efficiently, and linked to 6 neighbour chips through asynchronous links [19].…”

Wide learning: Using an ensemble of biologically-plausible spiking neural networks for unsupervised parallel classification of spatio-temporal patterns

“…One of the key reasons for this is the nature of the hardware commonly used in computing [4]. While there is much research focused on tackling this issue in hardware [5], [6], in this paper we propose a software-based model of an ensemble of unsupervised SNN for parallel, distributed processing of spatio-temporal data.…”