Spill code minimization via interference region spilling

Bergner, Peter; Dahl, Peter; Engebretsen, David Robert; O’Keefe, Matthew

doi:10.1145/258915.258941

Cited by 42 publications

(19 citation statements)

References 6 publications

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“…Studies based on the algorithm of Chaitin and colleagues [18][19][20] have developed spilling heuristics to reduce spill code. Kolt, Bergner, and their colleagues [21,22] subsequently further narrowed the interference live ranges into interference regions. Also, precise knowledge of the availability of registers allows spill code motion [23] to partially allocate registers.…”

Section: Previous Workmentioning

confidence: 99%

Achieving spilling-friendly register file assignment for highly distributed register files

Shih

et al. 2014

J Supercomput

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Distributed register file architectures divide registers into multiple sets, and it follows that the register files could be small. This can increase the frequency of spilling if register allocation encounters high register pressure, which will reduce the performance. That is, there is extra spilling to handle the pressure and results in performance decline. One of the factors that can produce high pressure is improper register file assignment. Register file assignment is a phase that assigns virtual registers to suitable register files and avoids communication costs. To reduce spilling in the phase of register file assignment, this paper proposes the SPIlling-FRiendly (SPIFR) method, which attempts to improve spilling by estimating the spilling cost from two aspects: assignment and spilling. We used MiBench and EEMBC benchmarks in experiments performed with the Open64-based compiler and a cycle-accurate instruction set simulator. The MiBench experimental results show that the SPIFR method improved the average cycle counts of the benchmarks by 6.0 %. For the kernels of the benchmarks, the method improved the average cycle counts by 20.5 % and reduced the average spilling ratio by 19.0 %. The results on the EEMBC benchmarks indicate that the method improved the cycle counts with the average speedup of 7.0 %, the speedup average of the kernel functions was 11.3 %, and the average reduction in the spilling ratio was 11.7 %, respectively. We conclude that the SPIFR method can reduce spilling and increase the performance.

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Section: Previous Workmentioning

confidence: 99%

Achieving spilling-friendly register file assignment for highly distributed register files

Shih

et al. 2014

J Supercomput

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“…So, the latency of each added edge is set to 1; 2. in the case of VLIW or EPIC/IA64, there exist reading and writing offsets. 3 Thus, for each added edge e = (u , v), the latency is set to…”

Section: An Algorithmic Heuristics For Reducing the Register Saturationmentioning

confidence: 99%

Register Saturation in Instruction Level Parallelism

Touati¹

2005

Int J Parallel Prog

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International audienceThe registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG. We mathematically study an approach which consists in managing the exact upper-bound of the register need for all the valid schedules of a considered DAG, independently of the functional unit constraints. We call this computed limit the register saturation (RS) of the DAG. Its aim is to detect possible obsolete register constraints, i.e., when RS does not exceed the number of available registers. If it does, we add some serial edges to the original DAG such that the worst register need does not exceed the number of available registers. We propose an appropriate mathematical formalism for this problem. Our generic processor model takes into account superscalar, VLIW and EPIC/IA64 architectures. Our deeper analysis of the problem and our formal methods enable us to provide nearly optimal heuristics and strategies for register optimization in the face of ILP

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“…Live range splitting is a technique for reducing the spill amount [Chow and Hennessy 1990;Kolte and Harrold 1993;Cooper and Simpson 1998;Bergner et al 1997;Briggs 1992;Lueh 1997;Appel and George 2001]. It splits long live ranges into shorter ones by inserting copies and load/stores at appropriate places.…”

Section: Live Range Splitting and Optimistic Coalescingmentioning

confidence: 99%

“…They can be roughly categorized into the during-coloring approach and the before-coloring approach, depending on when the splitting takes place [Lueh 1997]. The during-coloring approach splits uncolorable live ranges on demand during the coloring, generally in the color select phase [Chow and Hennessy 1990;Bergner et al 1997;Cooper and Simpson 1998]. On the other hand, the before-coloring approach splits live ranges in advance before the coloring starts [Briggs 1992;Appel and George 2001].…”

Section: Live Range Splitting and Optimistic Coalescingmentioning

confidence: 99%

Optimistic register coalescing

Park

Moon

2004

ACM Trans. Program. Lang. Syst.

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Graph-coloring register allocators eliminate copies by coalescing the source and target nodes of a copy if they do not interfere in the interference graph. Coalescing, however, can be harmful to the colorability of the graph because it tends to yield a graph with nodes of higher degrees. Unlike aggressive coalescing, which coalesces any pair of noninterfering copy-related nodes, conservative coalescing or iterated coalescing perform safe coalescing that preserves the colorability. Unfortunately, these heuristics give up coalescing too early, losing many opportunities for coalescing that would turn out to be safe. Moreover, they ignore the fact that coalescing may even improve the colorability of the graph by reducing the degree of neighbor nodes that are interfering with both the source and target nodes being coalesced. This article proposes a new heuristic called optimistic coalescing which optimistically performs aggressive coalescing, thus exploiting the positive impact of coalescing aggressively, but when a coalesced node is to be spilled, it is split back into separate nodes. Since there is a better chance of coloring one of those splits, we can reduce the overall spill amount.

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Spill code minimization via interference region spilling

Cited by 42 publications

References 6 publications

Achieving spilling-friendly register file assignment for highly distributed register files

Achieving spilling-friendly register file assignment for highly distributed register files

Register Saturation in Instruction Level Parallelism

Optimistic register coalescing

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