Speed, power and component density in multielement high-speed logic systems

Early, J.M.

doi:10.1109/isscc.1960.1157266

Cited by 18 publications

(3 citation statements)

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“…IEEE P 1500 standard has been reported by F. Dasilva , Y. Zorian et. al in [7]The origins of 3D dates back to 80's when James Early of Bell laboratories in [8] discussed 3D stacking of electronics and predicted that heat removal from such an integration would be the main concern. Research was also carried out by IBM, NEC, Siemens and Fraunhofer in 1990's.…”

Section: Brief Backgroundmentioning

confidence: 99%

Test Scheduling of Stacked 3D SoCs with Thermal Aware Considerations

Rawat¹,

Gupta²,

Singh³

2015

IJCA

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Today's electronic designs have become prone to errors and defects due to the ever increasing complexity and compactions. This has resulted into imparting of much more importance to VLSI testing. Testing is mandatory and has to be performed on each manufactured product. Low cost and good defect coverage are the basic goals of testing, which are again determined by fault models, test volume and time. Time depends on how the tests are scheduled. Test scheduling has therefore become an important area of research. The work here is devoted to test scheduling of 3D SoCs taking into account the severe challenge it faces for its adoption i.e. the thermal management problem. 3D technology fulfils the demand of faster and compact design but there is a sharp rise in power density in such arrangement. Due to vertical stacking in 3D technology, there is a sharp rise in temperature especially for the layers far from heat sink. Consequently formation of hotspots may occur which may lead to device failure. Testing dissipates more power than the functional power because of the high switching activity that takes place during testing. All this requires thermal aware based test scheduling so that temperature does not rise above limits. The method presented here involves a thermal aware test scheduling for a 3D Soc built up using floorplan of benchmark circuit d695 and few other examples. The modeling of 3D structure is done using resistors and explores conductance mode of heat transfer. The method has been compared with sequential test scheduling since no other work on similar lines is available to the best of knowledge of authors. The method shows a marked reduction in temperature rise and consequent elimination of hotspot formation.

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Section: Brief Backgroundmentioning

confidence: 99%

Test Scheduling of Stacked 3D SoCs with Thermal Aware Considerations

Rawat¹,

Gupta²,

Singh³

2015

IJCA

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show abstract

“…For the background it is worth mentioning that thermal analysis of vertically arranged circuits was done way back in 1960 [5] when James Early of Bell laboratories discussed 3D stacking and predicted that the main hurdle to its adoption would be the heat removal. The attraction of such an arrangement included the high packaging density obtainable, ability to integrate different technologies in one device.…”

Section: Thermal Analysismentioning

confidence: 99%

Thermal analysis and modeling of 3D integrated circuits for test scheduling

Rawat

Gupta

Singh

2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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A lot of present research is bei adoption of a new technology calThe demand of today is als heterogeneous integration of differ that a true SoC design can technology poses several proble ones being the removal of heat. Th comes into picture. One of the p the problems can be the spliting into more than one group and test as to take advantage of low amb the beginning of testing. The f adjusted and the effect on temperat

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“…However, while offering exciting opportunities, this new technology also brings about many new design challenges, among which the thermal problem is one of the major limiting factors. As pointed out by James Early, the total number of electronic elements that can be integrated within a system is constrained by the average power density [17] due to the thermal requirements. As shown in Fig.…”

Section: Motivationmentioning

confidence: 99%

Thermal management of 3D integrated circuits with microchannel-based liquid cooling

Qian¹

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Speed, power and component density in multielement high-speed logic systems

Cited by 18 publications

References 0 publications

Test Scheduling of Stacked 3D SoCs with Thermal Aware Considerations

Test Scheduling of Stacked 3D SoCs with Thermal Aware Considerations

Thermal analysis and modeling of 3D integrated circuits for test scheduling

Thermal management of 3D integrated circuits with microchannel-based liquid cooling

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