Speed Optimization of the AES Algorithm Using Pipeline Hardware Architecture

Punia, Dheeraj; Singh, Brahmjit

doi:10.1109/icces45898.2019.9002086

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2019 International Conference on Communication and Electronics Systems (ICCES) 2019

DOI: 10.1109/icces45898.2019.9002086

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Speed Optimization of the AES Algorithm Using Pipeline Hardware Architecture

Dheeraj Punia

Brahmjit Singh

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2023

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Speed Optimization of the AES Algorithm Using Pipeline Hardware Architecture

Cited by 1 publication

References 16 publications

FPGA Implementation Of a High Throughput Low Power Advanced Encryption Standard (AES-128) Cipher

FPGA Implementation Of a High Throughput Low Power Advanced Encryption Standard (AES-128) Cipher

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