Speculative tag access for reduced energy dissipation in set-associative L1 data caches

Bardizbanyan, Alen; Själander, Magnus; Whalley, David; Larsson-Edefors, Per

doi:10.1109/iccd.2013.6657057

Cited by 13 publications

(15 citation statements)

References 16 publications

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“…The analysis for selecting this range is described in prior work [Bardizbanyan et al 2013a]. For the given bitwidth range, we found that a speculative DFC access was attempted for 73.8% of the load operations and that the speculation success rate (no carry out) for these accesses was 97% for our benchmark suite.…”

Section: Accessing the Dfc Early In The Pipelinementioning

confidence: 91%

Designing a practical data filter cache to improve both energy efficiency and performance

Bardizbanyan

Själander

Whalley

et al. 2013

ACM Trans. Archit. Code Optim.

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Conventional Data Filter Cache (DFC) designs improve processor energy efficiency, but degrade performance. Furthermore, the single-cycle line transfer suggested in prior studies adversely affects Level-1 Data Cache (L1 DC) area and energy efficiency. We propose a practical DFC that is accessed early in the pipeline and transfers a line over multiple cycles. Our DFC design improves performance and eliminates a substantial fraction of L1 DC accesses for loads, L1 DC tag checks on stores, and data translation lookaside buffer accesses for both loads and stores. Our evaluation shows that the proposed DFC can reduce the data access energy by 42.5% and improve execution time by 4.2%. ACM Reference Format:Bardizbanyan, A., Själander, M., Whalley, D., and Larsson-Edefors, P. 2013. Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans.

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Section: Accessing the Dfc Early In The Pipelinementioning

confidence: 91%

Designing a practical data filter cache to improve both energy efficiency and performance

Bardizbanyan

Själander

Whalley

et al. 2013

ACM Trans. Archit. Code Optim.

Self Cite

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“…We use extracted energy estimates from a placed and routed RTL description of a 5-stage in-order processor including 16kB 4-way set-associative instruction and data caches [9] with 32B line size [5]. Although the implemented pipeline is simpler than the pipeline evaluated in this work, the energy for accessing the L1 DC is representative.…”

Section: Resultsmentioning

confidence: 99%

“…As a result, the load operations that can benefit from this approach will be close to the proposed ELD 3 technique. Speculative tag access allows many load operations to access L1 DC sequentially by making the tag match speculatively in an early stage of the pipeline [5].But this technique can only be applied to virtually indexed physically tagged (VIPT) L1 DCs.…”

Section: Related Workmentioning

confidence: 99%

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD<sup>3</sup>)

Bardizbanyan¹,

Själander²,

Whalley³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load operations for reduced access latency. This is required in order to resolve data dependencies as early as possible in the pipeline, which otherwise would suffer from stall cycles. A significant amount of energy is wasted due to this fast access, since the data can only reside in one of the ways. While it is possible to reduce L1 DC energy usage by accessing the tag and data memories sequentially, thereby activating only one data way on a tag match, this approach significantly increases execution time due to an increased number of stall cycles. We propose an early load data dependency detection (ELD 3 ) technique for in-order pipelines that can detect if the load has a data dependency with a subsequent instruction that will cause stall cycles. If there is no such dependency, then the tag and data accesses for the load are sequentially performed so that only the data way in which the data resides is accessed. If there is a dependency, then the tag and data arrays are accessed in parallel to avoid introducing additional stall cycles. For the MiBench benchmark suite, the ELD 3 technique enables about 49% of all load operations to access the L1 DC sequentially. In a 65-nm physical implementation using commercial SRAM blocks, the proposed technique reduces L1 DC energy by 13%.

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“…(Sensitivity Analysis) on the prediction accuracy, several efforts are made to improve the accuracy by employing PC-based prediction with feedback mechanism [20], way caching [21]. These techniques can work along with a fast speculative address generation [21], speculative tag access [22] etc., to improve the prediction accuracy further. Along with way-prediction techniques a few set-prediction techniques [23]- [25] are also proved to be effective for energy savings and performance improvement.…”

Section: Related Workmentioning

confidence: 99%

SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache

Majumder

Mutyam

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Conventionally, consecutively addressed blocks are mapped onto different sets in cache. In this work, we propose a new block address mapping, Set-First Fill (SFFMap), for pipelined L1 data caches wherein consecutively addressed data blocks are mapped onto the same set. This increases the inter-block spatial locality within the cache set. In order to exploit SFFMap, we propose to store and if possible, access the most recently used set in the cache's pipeline registers. Further, selective access (SSA) and selective update (SSU) techniques are proposed for setbuffer to increase the effectiveness of SFFMap. Our experimental evaluation for in-order and out-of-order processors with an 8-way set-associative data cache shows that SFFMap, together with SSA and SSU, achieves around 27% reduction in dynamic energy and 4-5% performance improvement. The proposed techniques need minor modifications to the existing hardware, making it an adoptable design.

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Speculative tag access for reduced energy dissipation in set-associative L1 data caches

Cited by 13 publications

References 16 publications

Designing a practical data filter cache to improve both energy efficiency and performance

Designing a practical data filter cache to improve both energy efficiency and performance

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD<sup>3</sup>)

SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache

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