Speculative Parallel Threading Architecture and Compilation

Abstract

Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its input data are ready. This technique appears particularly appealing for speeding up hardto-parallelize applications. Although various threadlevel speculation architectures and compilation techniques have been proposed by the research community, scalar applications remain difficult to be parallelized. It has not yet shown how well these applications can actually be benefited from threadlevel speculation and if the performance gain is significant enough to justify the required hardware support. In an attempt to understand and realize the potential gain with thread-level speculation especially for scalar applications, we proposed an SPT (Speculative Parallel Threading) architecture and developed an SPT compiler to generate optimal speculatively parallelized code. Our evaluation showed that with our SPT approach 10 SPECint2000 programs can achieve an average of 15.6% speedup on a two-core SPT processor by exploiting only loop parallelism. This paper describes the SPT architecture and the SPT compiler which performs aggressive costdriven loop selection and transformation, and presents our performance evaluation results.

A Survey on Thread-Level Speculation Techniques

“…The main disadvantage of these proposals is that, in general, for loops with irregular memory accesses and complex control flow, this solution does not obtain good predictions. Other works that use predictors are [Sohi et al 1995;Akkary and Driscoll 1998;Codrescu and Wills 1999a;Steffan et al 2002;Cintra and Torrellas 2002;Prabhu and Olukotun 2003;Li et al 2005;Fan et al 2012;Gao et al 2013].…”

“…Note that this solution may discard threads that have consumed values from the offending thread that have no relationship with the value that triggered the dependence violation. [Li et al 2005] tried to implement this ideas in hardware. [Colohan et al 2006] also used this kind of squashing mechanism in the context of databases (where restarting a thread leads to big performance losses), and used sub-threads to check for squashed threads. ]…”

“…SPT approach. [Li et al 2005] described an architecture specially designed to support scalar applications. This work also contains the design of a compiler specially developed for this architecture 5 .…”

Design and evaluation of a Thread-Level Speculation runtime library

“…The main disadvantage of these proposals is that, in general, for loops with irregular memory accesses and complex control flow, this solution does not obtain good predictions. Other works that use predictors are [4,52,55,84,96,167,208,233,235,239].…”

“…• Exclusive squashing: Only offending threads and those successors that have consumed any value generated by them are discarded and restarted. Li et al [167] tried to implement this ideas in hardware. Colohan et al [57] also used this kind of squashing mechanism in the context of databases (where restarting a thread leads to big performance losses), and used sub-threads to check for squashed threads.…”