Spectroscopic immersion ellipsometry study of the mechanism of Si/SiO2 interface annealing

Yakovlev, V. A.; Liu, Q.; Irene, E. A.

doi:10.1116/1.578166

Cited by 38 publications

(9 citation statements)

References 8 publications

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“…The most commonly used optical techniques are single wavelength and spectroscopic ellipsometry, 29,[70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85] reflectance difference spectroscopy ͑RDS͒, [86][87][88] second harmonic generation ͑SHG͒, [89][90][91][92][93][94][95][96][97] and Fourier transform infrared spectroscopy ͑FTIR͒. 82,98 -107 Ellipsometry is based on the measurement and subsequent modeling of changes in the polarization state of a light beam reflected from a sample surface, as is illustrated in Fig.…”

Section: A Optical Methodsmentioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

746

345

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The outstanding properties of SiO 2 , which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO 2 interface, which forms the heart of the modern metal-oxide-semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin ͑Ͻ4 nm͒ SiO 2 and Si-ON ͑silicon oxynitride͒ gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices will be manufactured with SiO 2 and Si-ON for the foreseeable future, continued scaling of integrated circuit devices, essentially the continued adherence to Moore's law, will necessitate the introduction of an alternate gate dielectric once the SiO 2 gate dielectric thickness approaches ϳ1.2 nm. It is hoped that this article will prove useful to members of the silicon microelectronics community, newcomers to the gate dielectrics field, practitioners in allied fields, and graduate students. Parts of this article have been adapted from earlier articles by the authors ͓L.

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Section: A Optical Methodsmentioning

confidence: 99%

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Green¹,

Gusev

Degraeve

et al. 2001

Journal of Applied Physics

746

345

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“…We have shown that the sensitivity is increased more than tenfold using the liquid ambient. 9 In our previous research, we investigated the evolution of the SiISiO 2 interface as a function of high temperature annealing (750-10000C) by SIE 10 and used the interface model shown in Fig. 2, which is also applicable to this study.…”

Section: Abstract (Maximum 200 Words)mentioning

confidence: 99%

Si/SiO2 interface studies by spectroscopic immersion ellipsometry and atomic force microscopy

Liu

Wall

Irene

1994

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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The dependence of the Si/SiO2 interface characteristics on the thickness and oxidation temperature for SiO2 films grown on different Si orientations was studied by spectroscopic immersion ellipsometry (SIE) and atomic force microscopy (AFM). Essentially, SIE uses liquids that match the refractive index of the films, thereby optically removing the films and consequently increasing the sensitivity to the interface. We show that as the thickness of the thermally grown SiO2 overlayer increases, the thickness of the suboxide layer at the interface also increases, and the average radius of the crystalline silicon protrusions (roughness) at the interface decreases for the three different Si orientations (100), (110), and (111), and two different oxidation temperatures (800 and 1000 °C) studied. The dependence of the interface roughness on the thickness of the SiO2 overlayer was confirmed by AFM. The results include unintentionally and intentionally roughened Si samples and are shown to be consistent with the commonly accepted Si oxidation model.

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“…Yakovlev et al reported on the near-interfacial properties using visible spectroscopic ellipsometry with the immersion method. 35,36 They assumed that the protrusions of silicon and the suboxide exist at the interface, and determined that the interfacial layer thickness and the volume fraction are 0.98ϩ0.34 nm and from 0.687 to 0.991, respectively, summed over oxide and suboxide. Translating their result to ours, a depolarization factor L of 0.6 using the relations aϭͱ2D/(4R) and Lϭa/(aϩ2), where the radius of protrusions, R, is 0.98 nm and the distance between protrusions D, is 4.4 nm, are obtained.…”

Section: Comparison With Other Resultsmentioning

confidence: 99%

Contribution of interface roughness to the infrared spectra of thermally grown silicon dioxide films

Ishikawa

Ogawa

Fujimura

1999

Journal of Applied Physics

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Spectroscopic immersion ellipsometry study of the mechanism of Si/SiO2 interface annealing

Cited by 38 publications

References 8 publications

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Si/SiO2 interface studies by spectroscopic immersion ellipsometry and atomic force microscopy

Contribution of interface roughness to the infrared spectra of thermally grown silicon dioxide films

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Spectroscopic immersion ellipsometry study of the mechanism of Si/SiO2 interface annealing

Cited by 38 publications

References 8 publications

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (&lt;4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Si/SiO2 interface studies by spectroscopic immersion ellipsometry and atomic force microscopy

Contribution of interface roughness to the infrared spectra of thermally grown silicon dioxide films

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Product

Resources

About

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits