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Introduction to Self-Aware Systems-on-ChipWe are seeing an increasing number of complex cyber-physical systems (CPS) deployed for various applications, such as road-traffic control involving communicating autonomous cars and infrastructure, or smart grids controlling energy delivery down to the individual device. These distributed applications follow common design objectives, such as energy-efficiency, and require guarantees for high availability, real time or safety. In this context, autonomy is crucial: multiple system goals varying over time need to be adaptively managed and objectives holistically coordinated. By empowering future CPS with self-awareness, these systems promise to dynamically adapt, learn, and manage unforeseen changes [6].

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“…The SCT hierarchy in Fig. 6.6 is successfully used to manage quality-of-service (QoS) goals within a power budget on an HMP in [18].…”

Section: Hierarchical Controllersmentioning

confidence: 99%

Reflecting on Self-Aware Systems-on-Chip

Donyanavard

Mück

Moazzemi

et al. 2020

A Journey of Embedded and Cyber-Physical Systems

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“…These techniques combine PID-like control techniques to various parts of the system, and provide empirical demonstrations of overall system behavior without taking domain knowledge into consideration. Recent work on optimal resource allocation focuses on designing sophisticated control systems using linear quadratic Gaussian control for example [42]- [44]. Unlike SLAMBooster, they also do not exploit application-specific properties to perform control.…”

Section: B Adaptive Resource Managementmentioning

confidence: 99%

SLAMBooster: An Application-Aware Online Controller for Approximation in Dense SLAM

Pei

Biswas

Fussell

et al. 2019

2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT)

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Simultaneous Localization and Mapping (SLAM) is the problem of constructing a map of a mobile agent's environment while localizing the agent within the map. Dense SLAM algorithms perform reconstruction and localization at pixel granularity. These algorithms require a lot of computational power, which has hindered their use on low-power resourceconstrained devices.Approximate computing can be used to speed up SLAM implementations as long as the approximations do not prevent the agent from navigating correctly through the environment. Previous studies of approximation in SLAM have assumed that the entire trajectory of the agent is known before the agent starts, and they have focused on offline controllers that set approximation knobs at the start of the trajectory. In practice, the trajectory is usually not known ahead of time, and allowing knob settings to change dynamically opens up more opportunities for reducing computation time and energy.In this paper, we describe SLAMBooster, an application-aware, online control system for dense SLAM that adaptively controls approximation knobs during the motion of the agent. SLAMBooster is based on a control technique called proportional-integralderivative (PID) controller but our experiments showed this application-agnostic controller led to an unacceptable reduction in localization accuracy. To address this problem, SLAMBooster also exploits domain knowledge for controlling approximation by performing smooth surface detection and pose correction.We implemented SLAMBooster in the open-source SLAM-Bench framework and evaluated it on more than a dozen trajectories from both the literature and our own study. Our experiments show that on the average, SLAMBooster reduces the computation time by 72% and energy consumption by 35% on an embedded platform, while maintaining the accuracy of localization within reasonable bounds. These improvements make it feasible to deploy SLAM on a wider range of devices.

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“…With augmented on-chip and cross-layer sensing and actuation capabilities, it supports adaptation per layer and multiple cooperative ODA loops to achieve multi-objective goals. SPECTR [18] is a new management approach for many-core processors that leverages formal supervisory control theory to decompose complex control problems into sub-problems that are solved by local controllers. A survey has been made covering recent advancements in self-aware platforms [8].…”

Section: Related Work Memory Schedulingmentioning

confidence: 99%

A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets

Song

Alavoine

Lin

2019

ACM Trans. Archit. Code Optim.

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In modern heterogeneous MPSoCs, the management of shared memory resources is crucial in delivering end-to-end QoS. Previous frameworks have either focused on singular QoS targets or the allocation of partitionable resources among CPU applications at relatively slow timescales. However, heterogeneous MPSoCs typically require instant response from the memory system where most resources cannot be partitioned. Moreover, the health of different cores in a heterogeneous MPSoC is often measured by diverse performance objectives. In this work, we propose the Self-Aware Resource Allocation framework for heterogeneous MP-SoCs. Priority-based adaptation allows cores to use different target performance and self-monitor their own intrinsic health. In response, the system allocates non-partitionable resources based on priorities. The proposed framework meets a diverse range of QoS demands from heterogeneous cores. Moreover, we present a runtime scheme to configure priority-based adaptation so that distinct sensitivities of heterogeneous QoS targets with respect to memory allocation can be accommodated. In addition, the priority of best-effort cores can also be regulated. This article is an extension of a conference paper: "SARA: Self-Aware Resource Allocation for Heterogeneous MPSoCs," published in DAC'18 (Song et al.). In particular, we extend our work in the following ways: -We add a new section to discuss the challenges of priority-based adaptation in the SARA framework. To deal with the challenges, we introduce a two-stage runtime configuration solution, including distributed self-configuration and global regulation, to accommodate best-effort cores and real-time cores that are particularly sensitive to memory allocation updates.-We expand the evaluation section to include more details on our simulation platform. We also present evaluation results on the runtime configuration scheme for the SARA framework.-In addition, a more comprehensive review of related work is provided in this paper to summarize prior efforts on memory scheduling and management.16:2 Y. Song et al. INTRODUCTIONModern heterogeneous MPSoCs [15,17] have been widely deployed in mobile devices thanks to their energy efficiency. These MPSoCs typically integrate a diverse collection of cores. Figure 1 depicts an example of a heterogeneous MPSoC. Besides general-purpose cores like the CPU for running applications, most heterogeneous cores are dedicated to certain functions, such as the GPU, the DSP, and the display. These cores have diverse notions of Quality-of-Service (QoS). For example, the GPU measures target real-time performance in terms of frame rate, the DSP demands the memory latency to remain below a certain limit, and the display requires sufficient bandwidth to refresh frames at a constant rate.To save cost and energy, heterogeneous cores commonly share resources, among which the sharing of the memory system including the network-on-chip (NoC) and the memory controller (MC) are the most challenging, because memory performance often has a direct and...

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Cited by 33 publications

References 72 publications

Reflecting on Self-Aware Systems-on-Chip

Reflecting on Self-Aware Systems-on-Chip

SLAMBooster: An Application-Aware Online Controller for Approximation in Dense SLAM

A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets

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