SpecPref: High Performing Speculative Attacks Resilient Hardware Prefetchers

Solanki, Tarun; Panda, Biswabandan

doi:10.1109/host54066.2022.9839828

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Another category, such as InvisiSpec [9], SafeSpec [24] and MuonTrap [25], designs a shadow structure to temporarily hold the data brought by speculative loads during transient execution, but they require many modifications to the existing hardware systems. Although SafeSpec [26] achieves a 3% performance improvement by avoiding cache pollution, its threat model is attacks on transient speculative execution, which are different from our threat model on cache timing side channel attacks. SpecPref [26] also aims at speculative execution vulnerabilities and prefetchers, but the role of the prefetchers in SpecPref is the source of the data leakage instead of the way of defense, which is a different threat model.…”

Section: B Microarchitectural Defensesmentioning

confidence: 85%

“…Although SafeSpec [26] achieves a 3% performance improvement by avoiding cache pollution, its threat model is attacks on transient speculative execution, which are different from our threat model on cache timing side channel attacks. SpecPref [26] also aims at speculative execution vulnerabilities and prefetchers, but the role of the prefetchers in SpecPref is the source of the data leakage instead of the way of defense, which is a different threat model.…”

Section: B Microarchitectural Defensesmentioning

confidence: 85%

See 1 more Smart Citation

PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender

Lit

Huang

Feng

et al. 2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Cache side channel attacks are increasingly alarming in modern processors due to the recent emergence of Spectre and Meltdown attacks. A typical attack performs intentional cache access and manipulates cache states to leak secrets by observing the victim's cache access patterns. Different countermeasures have been proposed to defend against both general and transient execution based attacks. Despite their effectiveness, they mostly trade some level of performance for security, or have restricted security scope. In this paper, we seek an approach to enforcing security while maintaining performance. We leverage the insight that attackers need to access cache in order to manipulate and observe cache state changes for information leakage. Specifically, we propose PREFENDER, a secure prefetcher that learns and predicts attack-related accesses for prefetching the cachelines to simultaneously help security and performance. Our results show that PREFENDER is effective against several cache side channel attacks while maintaining or even improving performance for SPEC CPU 2006 and 2017 benchmarks.

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