Specification and implementation of a cryptocoprocessor for ISDN

Sachs, W.; Wolter, S.

doi:10.1109/iscas.2000.857083

Cited by 1 publication

(4 citation statements)

References 2 publications

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“…The basic drawback of this system is the doubled covered area, compared with the proposed FPGA implementation. The presented work in [36] operates with very low frequency compared with the proposed. Although, no other information of the system throughput, and the needed clock cycles for the encryption/decryption process is given in [36].…”

Section: Synthesis Results and Evaluationmentioning

confidence: 97%

“…The presented work in [36] operates with very low frequency compared with the proposed. Although, no other information of the system throughput, and the needed clock cycles for the encryption/decryption process is given in [36]. These omissions in the reported synthesis results of [36] do not ensure a detailed comparison of this work with the proposed and the other conventional IDEA architectures [7,36,48].…”

Section: Synthesis Results and Evaluationmentioning

confidence: 97%

“…Although, no other information of the system throughput, and the needed clock cycles for the encryption/decryption process is given in [36]. These omissions in the reported synthesis results of [36] do not ensure a detailed comparison of this work with the proposed and the other conventional IDEA architectures [7,36,48]. In the work [48], the round keys are generated internally by using the basic transformation round architecture.…”

Section: Synthesis Results and Evaluationmentioning

confidence: 99%

“…The synthesis results prove that the integrated ciphers performance is very high, and better compared with ciphers separate implementations [4-7, 10, 12, 13, 18, 21, 29, 31, 36, 41, 44, 48], in most of the cases. IDEA architecture uses a modified transformation round, which minimizes the allocated area resources by about 30%, compared with other works [7,36,48]. DES proposed implementation performs better, with a range from 200 to 400%, compared with the other related works [5,13,21,44].…”

Section: Introductionmentioning

confidence: 94%

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Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

et al. 2006

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Communication protocols for wireless networks have specified security layers, with high-level encryption strength. The dedicated to security layer of Wireless Application Protocol (WAP), is the Wireless Transport Layer Security (WTLS). In this paper, an efficient architecture for the hardware implementation of WTLS is proposed. The introduced system supports bulk encryption, authentication and data integrity. The proposed architecture operates alternatively for a set of ciphers, IDEA, DES, RSA, D.H., SHA-1 and MD5. It is based on two reconfigurable design units: the Reconfigurable Authentication Unit and the Reconfigurable Integrity Unit. These units operate alternatively for different ciphers and achieve to allocate minimized resources, at the same time. The introduced security system has been implemented in an FPGA device. The supported ciphers performance is compared with previously published works, and it has been proven superior to them, in most of the cases. The system's synthesis results prove that the proposed architecture is a flexible and powerful solution for WTLS integration of today's and future wireless networks. The system can be applied to wireless communications servers and mobile devices also. Finally, the proposed architecture can be used as a powerful security engine, in WAP communication networks, with special security demands.

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Section: Synthesis Results and Evaluationmentioning

confidence: 97%