Special Section on Terascale Computing

Wesner, Stefan; Schubert, Lutz; Badía, Rosa M.; Rubio, Antonio Estepa; Paolucci, P.; Giorgi, Roberto

doi:10.1016/j.future.2015.07.015

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…There is still a slight inclination of part of the High-Performance Computing (HPC) community to embrace the data-flow ideas in order to speed up the execution of scientific applications. The reasons are mostly of a pragmatic nature rather than technical [1][2][3][4]. A dominant reason why the HPC community and, in particular, the applications programmers do not pay more attention to the advanced data-flow architecture ideas is due to the fact that, in the past, very highperformance data-flow systems of commercial grade were not readily available on the market.…”

Section: Introductionmentioning

confidence: 99%

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

Verdoscia

Giorgi

2016

Mathematical Problems in Engineering

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We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the Data-Flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations.

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Section: Introductionmentioning

confidence: 99%

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

Verdoscia

Giorgi

2016

Mathematical Problems in Engineering

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“…Nevertheless, efficiently scaling the performance of a computing system while maintaining easy programmability is still an open problem [8].…”

Section: Introductionmentioning

confidence: 99%

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Giorgi

2015

2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing

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Embedded System toolchains are highly customized for a specific System-on-Chip (SoC).\ud When the application needs more performance, the designer is typically forced\ud to adopt a new SoC and possibly another toolchain.\ud The rationale for not scaling performance by using, e.g., two SoCs, is\ud that maintining most of the operations on-chip may allow for higher energy efficiency.\ud We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC.\ud This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards.\ud A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer.\ud In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach

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Exploring Future Many-Core Architectures

Giorgi

2017

Advances in Computers

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Special Section on Terascale Computing

Cited by 6 publications

References 5 publications

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Exploring Future Many-Core Architectures

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