Spec Cpu2017

Bucek, James; Lange, Klaus-Dieter; Kistowski, Jóakim von

doi:10.1145/3185768.3185771

Cited by 175 publications

(20 citation statements)

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“…We used the SPEC CPU 17 [12] benchmarks and Boost library [15] as the datasets for learning the representations. The programs in these benchmarks are converted to LLVM IR by varying the compiler optimization levels (-O[0-3], -Os, -Oz) at random.…”

Section: Resultsmentioning

confidence: 99%

IR2V EC

VenkataKeerthy

Aggarwal

Jain

et al. 2020

ACM Trans. Archit. Code Optim.

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We propose IR2V EC , a Concise and Scalable encoding infrastructure to represent programs as a distributed embedding in continuous space. This distributed embedding is obtained by combining representation learning methods with flow information to capture the syntax as well as the semantics of the input programs. As our infrastructure is based on the Intermediate Representation (IR) of the source code, obtained embeddings are both language and machine independent. The entities of the IR are modeled as relationships, and their representations are learned to form a seed embedding vocabulary . Using this infrastructure, we propose two incremental encodings: Symbolic and Flow-Aware . Symbolic encodings are obtained from the seed embedding vocabulary , and Flow-Aware encodings are obtained by augmenting the Symbolic encodings with the flow information. We show the effectiveness of our methodology on two optimization tasks (Heterogeneous device mapping and Thread coarsening). Our way of representing the programs enables us to use non-sequential models resulting in orders of magnitude of faster training time. Both the encodings generated by IR2V EC outperform the existing methods in both the tasks, even while using simple machine learning models. In particular, our results improve or match the state-of-the-art speedup in 11/14 benchmark-suites in the device mapping task across two platforms and 53/68 benchmarks in the thread coarsening task across four different platforms. When compared to the other methods, our embeddings are more scalable , is non-data-hungry , and has better Out-Of-Vocabulary (OOV) characteristics .

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Section: Resultsmentioning

confidence: 99%

IR2V EC

VenkataKeerthy

Aggarwal

Jain

et al. 2020

ACM Trans. Archit. Code Optim.

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“…The impact of the CFS and UFS prediction on energy consumption relies on the PKG (package) energy consumption measurement. For the evaluations, we used applications from the SPEC CPU2017 benchmark suite [8]. Each experimental run lasts for 30 seconds.…”

Section: Methodsmentioning

confidence: 99%

“…The models enable the user to specify the maximum acceptable performance loss while conserving energy by choosing a suitable core/uncore frequency. We validated the models on the Intel Xeon E5-2620 Processor and applications from the SPEC2017 suite [8]. • We propose a learning model that predicts the change in performance of currently running, pre-optimized applications when one or more applications get replaced by others.…”

Section: Introductionmentioning

confidence: 99%

Performance-Energy Trade-off in Modern CMPs

Abera

Balakrishnan

Kumar

2020

ACM Trans. Archit. Code Optim.

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Chip multiprocessors (CMPs) are ubiquitous in all computing systems ranging from high-end servers to mobile devices. In these systems, energy consumption is a critical design constraint as it constitutes the most significant operating cost for computing clouds. Analogous to this, longer battery life continues to be an essential user concern in mobile devices. To optimize on power consumption, modern processors are designed with Dynamic Voltage and Frequency Scaling (DVFS) support at the individual core as well as the uncore level. This allows fine-grained control of performance and energy. For an n core processor with m core and uncore frequency choices, the total DVFS configuration space is now m (n+1) (with the uncore accounting for the + 1). In addition to that, in CMPs, the performance-energy trade-off due to core/uncore frequency scaling concerning a single application cannot be determined independently as cores share critical resources like the last level cache (LLC) and the memory. Thus, unlike the uni-processor environment, the energy consumption of an application running on a CMP depends not only on its characteristics but also on those of its co-runners (applications running on other cores). The key objective of our work is to select a suitable core and uncore frequency that minimizes power consumption while limiting application performance degradation within certain pre-defined limits (can be termed as QoS requirements). The key contribution of our work is a learning-based model that is able to capture the interference due to shared cache, bus bandwidth, and memory bandwidth between applications running on multiple cores and predict near-optimal frequencies for core and uncore.

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“…To understand how the CPU consumes electrical power, it is necessary to study the relationship between its way of operating and the amount of voltage / amperage expended. Thus, to measure its power consumption, SPEC CPU2017 [19] performs stress operations while studying the use of voltage and amperage according to the type of benchmark. On the other hand, SpeedStep [20] shows the relationship between the clock frequency and the energy consumed.…”

Section: Cpu Analysismentioning

confidence: 99%

The Architecture of Kaligreen V2: A Middleware Aware of Hardware Opportunities to Save Energy

Valera

Dalmau²,

Roose³

et al. 2019

2019 Sixth International Conference on Internet of Things: Systems, Management and Security (IOTSMS)

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Nowadays, energy saving in the use of information technologies is a very important issue both from the economic and sustainability point of view. Many scientists investigate methods to save energy at different application levels (cloud: i.e. architectures, grid: i.e. middlewares and frameworks and hardware management: i.e. operating systems) and many of them agree on the strategy of executing programs, processes or virtual machines only using the time and resources that are strictly necessary. For this, it is necessary to plan strategies for deployment and relocation of processes; but always taking into account hardware repercussions and the knowledge of the architecture and applications behavior. On the other hand, it has already been demonstrated that the use of microservices brings numerous advantages in availability and efficiency; but we do not find many jobs that exploit this technique on the energy level. In this article, we present the architecture of a middleware for distributed microservices-based applications, which allows any negotiation-based scheduling algorithm to duplicate or move microservices from one device to another in a non-centralized way for energy savings, taking into account the consumption characteristics of the microservices and the capabilities that the hardware components offer.

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Spec Cpu2017

Cited by 175 publications

References 0 publications

IR2V EC

IR2V EC

Performance-Energy Trade-off in Modern CMPs

The Architecture of Kaligreen V2: A Middleware Aware of Hardware Opportunities to Save Energy

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