Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency

Lucas, Jan; Andersch, Michael; Alvarez-Mesa, Mauricio; Juurlink, Ben

doi:10.1145/2811402

Cited by 5 publications

(4 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The analysis shows the maximum, average and minimum PSNR losses (red, green, and blue lines, respectively), alongside the percentile of intra pixels (purple line) for each decoded B-frame. The first important information from these plots is that the PSNR losses within an intra period resemble a negative quadratic function, with highest loss values being achieved in the middle frame (16) of the intra period between GoPs.…”

Section: Results For Random Access Configurationmentioning

confidence: 99%

“…In this sense, approximate storage is a promising paradigm for improving access time, energy consumption, memory cell density and lifetime, among others [10] [13] [14] [15]. It can be implemented through a variety of techniques based on the target memory technology, such as reducing the refresh rate in DRAM modules [16][17][18], increasing STT-RAM's read pulse current magnitude [10,19], reducing the SET/RESET iteration number [10] of PCM memories, among others. Such gains come at the cost of reduced reliability in the stored, read and/or written data, by subjecting it to the possibility of errors and, consequently, to the loss of quality in the results obtained from the target application, producing less accurate or lower quality results.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

VVC decoder intra prediction using approximate storage: an error resilience evaluation

Isquierdo,

Soares,

Sampaio

et al. 2023

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding (VVC) decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used Bit Error Rate (BER) values from literature for Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM) technologies. We perform an error resilience evaluation based on Peak signal-to-noise ratio (PSNR) and Structural Similarity (SSIM) for twelve video sequences, considering different decoding settings, with four Quantization Parameters (QPs), two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on VVC Decoder Intra Prediction Using Approximate Storage: an Error Resilience Evalu video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences.

show abstract

Section: Results For Random Access Configurationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

VVC decoder intra prediction using approximate storage: an error resilience evaluation

Isquierdo,

Soares,

Sampaio

et al. 2023

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Since the threads in a sub-warp are executed by all the SIMD lanes in synchrony, it is also called a spatial sub-warp. On the other hand, those warp threads that are executed by the same SIMD lane in consecutive execution round form a temporal sub-warp [24]. Thus, the SIMT co-processor introduces a third component, a spatial sub-warp context dispatcher, which prepares the current CPU thread ID, warp instruction, and PC for a spatial sub-warp execution, and as a result runs a warp in the consecutive execution of spatial sub-warps.…”

Section: Dual Mode Cpu Architecturementioning

confidence: 99%

Enabling SIMT Execution Model on Homogeneous Multi-Core System

Chen

2018

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Single-instruction multiple-thread (SIMT) machine emerges as a primary computing device in high-performance computing, since the SIMT execution paradigm can exploit data-level parallelism effectively. This article explores the SIMT execution potential on homogeneous multi-core processors, which generally run in multiple-instruction multiple-data (MIMD) mode when utilizing the multi-core resources. We address three architecture issues in enabling SIMT execution model on multi-core processor, including multithreading execution model, kernel thread context placement, and thread divergence. For the SIMT execution model, we propose a fine-grained multithreading mechanism on an ARM-based multi-core system. Each of the processor cores stores the kernel thread contexts in its L1 data cache for per-cycle thread-switching requirement. For divergence-intensive kernels, an Inner Conditional Statement First (ICS-First) mechanism helps early re-convergence to occur and significantly improves the performance. The experiment results show that effectiveness in data-parallel processing reduces on average 36% dynamic instructions, and boosts the SIMT executions to achieve on average 1.52× and up to 5× speedups over the MIMD counterpart for OpenCL benchmarks for single issue in-order processor cores. By using the explicit vectorization optimization on the kernels, the SIMT model gains further benefits from the SIMD extension and achieves 1.71× speedup over the MIMD approach. The SIMT model using in-order superscalar processor cores outperforms the MIMD model that uses superscalar out-of-order processor cores by 40%. The results show that, to exploit data-level parallelism, enabling the SIMT model on homogeneous multi-core processors is important.

show abstract

“…One of these levels should be an operation considered free from errors. Several proposed architectures [23,70,75,116] separate memory regions by reliability levels to isolate some data from errors. AxRAM is compatible with the architectural model of Truffle [23], but without the usage of ISA extensions, which would demand changes in some level of the application.…”

Section: Architectural Modelmentioning

confidence: 99%

Software and hardware interfaces for approximate memories

Fabrício Filho

View full text Add to dashboard Cite

I would like to thank the many people that give me support during this Ph.D.To my wife, Aline Maria Gonçalves Fabrício, for walking alongside me on this journey giving me support, and making me happy every day.To my advisor Lucas Wanner, for all the mentoring and guidance that were fundamental in formulating research questions and in my professional development.To Isaías Bittencourt Felzmann, for the feedback, ideas, collaborations on manuscripts, and the several discussions about the topics of this research.To Rodolfo Azevedo, for the support that improves the contributions of this work.

show abstract

Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency

Cited by 5 publications

References 31 publications

VVC decoder intra prediction using approximate storage: an error resilience evaluation

VVC decoder intra prediction using approximate storage: an error resilience evaluation

Enabling SIMT Execution Model on Homogeneous Multi-Core System

Software and hardware interfaces for approximate memories

Contact Info

Product

Resources

About