Spatial division multiplexing

Leroy, Anthony; Marchal, Pierre; Shickova, A.; Catthoor, F.; Robert, Frédéric; Verkest, D.

doi:10.1145/1084834.1084858

Cited by 40 publications

(2 citation statements)

References 10 publications

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“…In particular, they take advantage of the abundance of wires in current and expected deep sub-micron technologies. Carara et al based their work in spatial division multiplexing (SDM) introduced by Leroy et al [16] and Lane Division Multiplexing (LDM) technique introduced by Wolkotte et al [28]. SDM and LDM basically increase the number of wires between switches to assign different bandwidth resources to each channel at the cost of increasing the critical path.…”

Section: Related Work For Cmp Switchesmentioning

confidence: 99%

A low-latency modular switch for CMP systems

Roca

Flich

Silla

et al. 2011

Microprocessors and Microsystems

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As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies.In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10 to 21%. Network latency is reduced in a range from 11 to 15%.

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Section: Related Work For Cmp Switchesmentioning

confidence: 99%

A low-latency modular switch for CMP systems

Roca

Flich

Silla

et al. 2011

Microprocessors and Microsystems

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show abstract

“…'s , DSPIN , artNoC , and ALPIN are the architectures providing both GT and BE services. SPIN , HERMES , RaSoC , and spatial division multiplexing NoC are a few BE‐based NoC architectures. Meanwhile, aSOC , OCTAGON , Nexus , QNoC , PNoC , cross‐road interconnection architecture , HIBI , ProtoNoC , TTNoC , MoCSYS , Aelite and dAElite are NoC architectures providing GT‐based services.…”

Section: Introductionmentioning

confidence: 99%

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Sethi

Hussin

Hamid

2018

IEEJ Transactions Elec Engng

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Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques.

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Clustered NOC, a suitable design for group communications in Network on Chip

Seifi

Eshghi

2012

Computers & Electrical Engineering

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Spatial division multiplexing

Cited by 40 publications

References 10 publications

A low-latency modular switch for CMP systems

A low-latency modular switch for CMP systems

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Clustered NOC, a suitable design for group communications in Network on Chip

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