Spatial: a language and compiler for application accelerators

Abstract

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for productivity and are difficult to target from higher level languages. HLS tools are more productive, but offer an ad-hoc mix of software and hardware abstractions which make performance optimizations difficult. In this work, we describe a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators. We describe Spatial's hardwarecentric abstractions for both programmer productivity and design performance, and summarize the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning. We demonstrate the language's ability to target FPGAs and CGRAs from common source code. We show that applications written in Spatial are, on average, 42% shorter and achieve a mean speedup of 2.9× over SDAccel HLS when targeting a Xilinx UltraScale+ VU9P FPGA on an Amazon EC2 F1 instance.

Automatically exploiting the memory hierarchy of GPUs through just-in-time compilation

“…In addition, several parallel programming frameworks exist [11,17,23,29,38,44,45,47] that enable the compilation of domain-specific languages on GPUs. Lift [26,46] extends its existing data parallel primitive types to accommodate loop tiling (e.g., slide,pad) and its low-level OpenCL with local memory (e.g., toLocal) allocation for stencil computations.…”

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

“…Spatial [21] is mainly a domain-specific language embedded in Scala, tightly connected to the Chisel hardware description language [23]. The language provides a very high level of abstraction to design accelerators and targets not only various FPGA accelerator platforms (of both Intel and Xilinx), but also CGRA-like and ASIC targets.…”

“…Embedded domain-specific languages provide promising alternatives, e.g. [21,23] on the near-term, while valiant efforts to support designing new HDLs without being embedded in another language have very recently been presented, e.g. in [28].…”

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…More importantly, Plasticine targets floating-point intensive applications, which is also shown in their evaluation (only three out of 13 applications are integer only). Plasticine is programmable using Spatial [134]-a custom language based on patterns for dataflow computing.…”