Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA

Sigurbergsson, Bjorn; Hogervorst, Tom; Qiu, Tong; Nane, Răzvan

doi:10.1109/asap.2019.00-30

Cited by 12 publications

(5 citation statements)

References 14 publications

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“…COO format is applied to [12] and [14], which has an intuitive format to utilize. CSR format is selected in this work and [13] to reduce memory size compared to COO format for common datasets which are not hyper-sparse. The SpMV accelerator in [14] selects 20-bit to 26-bit fixed-point precision for PageRank acceleration, while working on the newly proposed FP16 to FP32 transprecision scheme has shown higher accuracy.…”

Section: Resultsmentioning

confidence: 99%

“…To reduce the memory overhead, [12] divided the SpMV algorithm into two steps and used parallel floating-point multipliers, focusing on high-performance computing for large and hyper-sparse datasets. Matrix partitioning scheme was also proposed to accelerate SpMV operation [13]. Partitioning of the sparse matrix using Compressed Sparse Row (CSR) format enabled parallel computation.…”

Section: Introductionmentioning

confidence: 99%

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Multi-Mode SpMV Accelerator for Transprecision PageRank With Real-World Graphs

Kim

Lee

et al. 2023

IEEE Access

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With the development of Internet networks, the PageRank algorithm, which was initially developed to recommend important pages in Google's web search systems, is widely used as the basis of various ranking systems in graph processing fields. However, PageRank algorithm requires Sparse Matrix-Vector Multiplication (SpMV) repeatedly which becomes main bottleneck for the calculation. In this study, we present the multi-mode SpMV accelerator for half-to-single transprecision PageRank with real-world graphs. To support transprecision, where the operation performs in half-precision (FP16) initially and changes its precision to single-precision (FP32), the proposed multi-mode SpMV accelerator can perform both dual FP16 mode and single FP32 mode. In dual FP16 mode, the proposed accelerator performs two FP16 SpMV in parallel, and in single FP32 mode, it performs one FP32 SpMV with the same hardware resources. Also, for the reduction of memory footprint, the proposed accelerator supports the Compressed Sparse Row (CSR) format. In addition, dual-issue accumulator and multi-mode transprecision multiplier are presented to support both FP16 and FP32 modes. Validation of the proposed transprecision PageRank algorithm is performed with four real-world graph datasets, resulting in a low 0-4% error rate and 1.3×-1.9× speedup compared to single-precision PageRank computation without transprecision.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multi-Mode SpMV Accelerator for Transprecision PageRank With Real-World Graphs

Kim

Lee

et al. 2023

IEEE Access

View full text Add to dashboard Cite

show abstract

“…To increase the scalability of our design and allow it to work on larger matrices, we will use sparstitioning [16]. Sparstitioning is a method for splitting both the matrix and the vector of a matrix-vector operation into partitions, so that no unnecessary data is read during the running of the operation on each partition.…”

Section: E Sparstitioningmentioning

confidence: 99%

Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs

Hogervorst,

Qiu,

Marchiori

et al. 2021

Preprint

Self Cite

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Scientific computing is at the core of many High-Performance Computing (HPC) applications, including computational flow dynamics. Because of the uttermost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. A Field-Programmable Gate Array (FPGA) is a reconfigurable hardware accelerator that is fully customizable in terms of computational resources and memory storage requirements of an application during its lifetime. Therefore, it is an ideal candidate to accelerate scientific computing applications because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers found in scientific libraries. In this paper, we study the potential of using FPGA in HPC because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we first propose a novel ILU0 preconditioner tightly integrated with a BiCGStab solver kernel designed using a mixture of High-Level Synthesis (HLS) and Register-Transfer Level (RTL) hand-coded design. Second, we integrate the developed preconditioned iterative solver in Flow from the Open Porous Media (OPM) project, a state-of-the-art open-source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both standalone mode and integrated into the reservoir simulator that includes all the on-chip URAM and BRAM, on-board High-Bandwidth Memory (HBM), and off-chip CPU memory data transfers required in a complex simulator software such as OPM's Flow. We evaluate the performance on the Norne field, a real-world case reservoir model using a grid with more than 10 5 cells and using 3 unknowns per cell, and we find that the FPGA is on par with the CPU execution and 3 times slower than the GPU implementation when comparing only the kernel executions.

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“…To increase the scalability of our design and allow it to work on larger matrices, we will use sparstitioning [27]. Sparstitioning is a method for splitting both the matrix and the vector of a matrixvector operation into partitions so that no unnecessary data is read during the running of the operation on each partition.…”

Section: Sparstitioningmentioning

confidence: 99%

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Hogervorst

Nane

Marchiori³

et al. 2021

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the utmost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. Field-Programmable Gate Arrays could accelerate scientific computing because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers. In this article, we study the potential of using Field-Programmable Gate Arrays in High-Performance Computing because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we propose a novel Sparse Matrix-Vector multiplication unit and an ILU0 preconditioner tightly integrated with a BiCGStab solver kernel. We integrate the developed preconditioned iterative solver in Flow from the Open Porous Media project, a state-of-the-art open source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both stand-alone mode and integrated in the reservoir simulator, using the NORNE field, a real-world case reservoir model using a grid with more than 10 5 cells and using three unknowns per cell.

show abstract

Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA

Cited by 12 publications

References 14 publications

Multi-Mode SpMV Accelerator for Transprecision PageRank With Real-World Graphs

Multi-Mode SpMV Accelerator for Transprecision PageRank With Real-World Graphs

Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

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