SparseCore: stream ISA and processor specialization for sparse computation

Abstract

Computation on sparse data is becoming increasingly important for many applications. Recent sparse computation accelerators are designed for specific algorithm/application, making them inflexible with software optimizations. This paper proposes SparseCore, the first general-purpose processor extension for sparse computation that can flexibly accelerate complex code patterns and fast-evolving algorithms. We extend the instruction set architecture (ISA) to make stream or sparse vector first-class citizens, and develop efficient architectural components to support the stream ISA. The novel ISA extension intrinsically operates on streams, realizing both efficient data movement and computation. The simulation results show that SparseCore achieves significant speedups for sparse tensor computation and graph pattern computation. CCS CONCEPTS• Computer systems organization → Architectures.

Software Systems Implementation and Domain-Specific Architectures towards Graph Analytics

“…Current ASIC-based graph mining accelerators all use the patternaware methodology to conduct graph mining applications, for the bounded memory footprint and inherent high concurrency. Existing research all adopt software/hardware codesigns to mapping graph mining applications to hardware logic, from algorithm-level mapping [41] to instruction level extensions [177].…”

“…There are also works to explore instruction set architecture (ISA) and corresponding hardware designs specialized for graph mining. SparseCore [177,180] propose the stream instruction set extension which represents the core computational operations in graph mining. Specifically, a stream is defined as a sparse vector in SparseCore.…”

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra

“…Graph pattern matching: Intersection between the sparse adjacency vectors of graph nodes can be leveraged to identify and count subgraph embeddings and assess the similarity of graphs [6]. Thus, SSSRs may be used to accelerate graph pattern matching workloads in fields like computer vision and drug discovery.…”

“…In machine learning (ML), sparsification can significantly reduce the operations and memory required for a given inference accuracy [4]; while some approaches target sparsedense compute by sparsifying only weights, others also exploit activation sparsity. Graphs, commonly represented as highly sparse matrices, are operands in both sparsedense and sparse-sparse workloads such as PageRank [5] and triangle counting [6].…”

“…While recent CPU, GPU, and accelerator works improve sparse workload performance, they are limited by their lack of generality or large microarchitectural impact. Most general-purpose instruction set architecture (ISA) extensions consider only one-sided sparsity [8], [9], and those targeting sparse-sparse workloads incur large area impacts and cannot efficiently handle the former [6]. Sparse ML solutions often rely on custom, domain-specific formats and low or structured sparsity [10], [11], while more general sparse LA accelerators [12], [13] incur significant silicon area impacts compared to their host systems and other solutions.…”