Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

Jang, Jaeshin; Shin, Wongyu; Choi, Jungwhan; Kim, Yongju; Kim, Lee-Sup

doi:10.1109/tc.2018.2881137

Cited by 7 publications

(3 citation statements)

References 33 publications

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“…the simulation results of the 4-cores/1-channel setting in this paper because the use of multiple cores causes an increase in both the memory access and the channel, and eventually the memory access per channel is maintained at a similar level through channel interleaving. For WDE modeling, counterbased modeling is used, and referring to the threshold value reported in SIWC [30] (i.e., 5K-10K), the threshold value T is set to a fairly conservative value of 1K to cover even the situation in which write disturbance becomes more severe as the technology node shrinks in the future.…”

Section: A Experimental Methodologymentioning

confidence: 99%

“…The probabilistic model assumes that WDE occurs with a fixed probability for every RESET operation. However, studies have shown that counter-based modeling is more plausible than probabilistic modeling [21], [22]. Counter-based modeling means that WDE occurs when the cumulative time of the disturbance exposure in one cell exceeds a certain value.…”

Section: B Write Disturbance Errors In Pcmmentioning

confidence: 99%

“…The probabilistic model models WDE with a probability of 0.01 for every RESET, while the counter-based model definitively generates WDE at the 100th RESET. In this paper, we use counter-based modeling as in [21], [22].…”

Section: B Write Disturbance Errors In Pcmmentioning

confidence: 99%

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WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory

et al. 2022

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Phase-change memory (PCM) is a promising non-volatile memory device due to its attractive properties such as fast access time and byte-addressability. However, PCM is still difficult to be used as a main memory because of its weakness in endurance and write disturbance. Conventional wearleveling algorithms have attempted to handle short endurance, but they have not addressed the issue of write disturbance even though both issues are caused by write operations to PCM. This paper proposes a wear-leveling algorithm that addresses not only the endurance, but also the write disturbance. From the observation that the write disturbance errors and short endurance issues mostly take place in hot addresses, the proposed algorithm first detects hot addresses and maps them to 'hot' regions, which are customized memory regions designed to be robust to write disturbance errors and to support effective wear-leveling. The 'hot' region is not fixed to a specific part, but it moves over an entire memory space to make every cell belong to 'hot' regions in a uniform manner. On the other hand, cold addresses are mapped in 'normal' memory regions by simple linear mapping to reduce the hardware overhead. The proposed algorithm can reduce the write disturbance errors by more than 70% with only a slight instruction per cycle (IPC) degradation. Moreover, the wear-leveling performance is also enhanced by more than 3% compared to other wear-leveling algorithms.

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Section: A Experimental Methodologymentioning

confidence: 99%

Section: B Write Disturbance Errors In Pcmmentioning

confidence: 99%