Space-time adaptive processing on the Mesh Synchronous Processor

McMahon, J. S.; Teitelbaum, K.

doi:10.1109/ipps.1996.508140

Cited by 10 publications

(2 citation statements)

References 4 publications

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“…A substantial number of papers have been published in this area, both for sonars (see, e.g., [2,3]) as well as radars (see, e.g., [4,5]). There has also been growing interest in implementing "multidimensional" FFTs on parallel processors [6].…”

Section: Corner Turning In Fft Bfmentioning

confidence: 99%

Elimination of corner-turning in FFT-based sonar array beamforming

Barhen

Humble

Traweek

2008

The Journal of the Acoustical Society of America

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The emergence of ultra-low power multicore processors will open unprecedented opportunities for implementing sophisticated signal processing algorithms faster and within a much lower energy budget. In that context, the concept of "corner turning" has been, for many decades, at the heart of array beamforming via Fourier transforms. As widely reported in the open literature (both for sonars and radars), the computational sequence involving corner turning operations, i.e., the sequence: temporal Fourier transforms data cube corner turning spatial Fourier transforms, constitutes a major obstacle to achieving high-performance and lower power dissipation (by reducing the number memory accesses). To date, leading industry providers still include explicit corner turning stages in their computational flow architectures for multidimensional array processing. The primary innovation reported in this paper addresses the development of a computational scheme that avoids altogether the corner turning stage. We discuss its implementation on currently available IBM CELL multicore technology and provide initial timing results.

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Section: Corner Turning In Fft Bfmentioning

confidence: 99%

Elimination of corner-turning in FFT-based sonar array beamforming

Barhen

Humble

Traweek

2008

The Journal of the Acoustical Society of America

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“…The Intel Xeon Phi 72x0 (KNL -Knights Landing) processor represents an important contribution in a long-line of manycore processors [1]- [4] with high-core count (≥64), large number of vector units (≥128), tiled physical layout, and high speed memory combined with significant amounts of DRAM [5], [6] (see Figures 1 and 2). The Xeon Phi is ideally suited to applications that perform many vector operations.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Xeon Phi for Interactive Data Analysis

Byun

Klein

Milechin³

et al. 2019

2019 IEEE High Performance Extreme Computing Conference (HPEC)

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The Intel Xeon Phi manycore processor is designed to provide high performance matrix computations of the type often performed in data analysis. Common data analysis environments include Matlab, GNU Octave, Julia, Python, and R. Achieving optimal performance of matrix operations within data analysis environments requires tuning the Xeon Phi OpenMP settings, process pinning, and memory modes. This paper describes matrix multiplication performance results for Matlab and GNU Octave over a variety of combinations of process counts and OpenMP threads and Xeon Phi memory modes. These results indicate that using KMP_AFFINITY=granlarity=fine, taskset pinning, and all2all cache memory mode allows both Matlab and GNU Octave to achieve 66% of the practical peak performance for process counts ranging from 1 to 64 and OpenMP threads ranging from 1 to 64. These settings have resulted in generally improved performance across a range of applications and has enabled our Xeon Phi system to deliver significant results in a number of real-world applications.

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