SP&amp;R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes

Lee, Daeyeal; Park, Dongwon; Ho, Chester S.; Kang, Ilgweon; Kim, Ha Young; Gao, Sicun; Lin, Bill; Cheng, Chung‐Kuan

doi:10.1109/tcad.2020.3037885

Cited by 16 publications

(14 citation statements)

References 37 publications

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“…To explore the scaling impact of many-tier VFETs on cell-level and block-level area, we select and generate 30 representative SDCs [33], [34] as specified in Table III for many-tier 7T VFET architecture with the number of tiers ranging 1-4 tiers by using ASAP7 [35] SDC netlists. We also generate 4.5T GAA Nanosheet FET (GAAFET) SDCs with buried power rails by scaling 4.5T FinFET SDCs [36], based on the effective width ratio [37] between FinFET and Nanosheet structures with the concurrent P&R framework [20] for the comparison with VFETs.…”

Section: Resultsmentioning

confidence: 99%

“…5 tracks), location of FETs (i.e., 2 nd /4 th horizontal tracks for P-FET/N-FET), and conditional design rules with [25] to compare our proposed concurrent P&R results to the known results for the conventional sequential P&R approach. The conditional design rule [20], [29] parameters are specified (MAR/EOL/VR/PRL/SHR/MPO=1/0/0/1/1/2) to have the same routing results as [25] for fair comparisons 4 .…”

Section: Resultsmentioning

confidence: 99%

“…Given netlist information and cell architecture, our framework directly obtains an optimal solution that precisely satisfies the constraints of transistor placement, in-cell routing, and conditional design rules. The individual placement and routing problems combine into the dynamic formulation targeting conditional pin allocation (i.e., DPA) [20]. The notations are shown in Table I.…”

Section: A Overview Of Vfet Sdc Synthesis Frameworkmentioning

confidence: 99%

“…We implement flow formulations and dynamic pin allocation (DPA) constraints for the concurrent P&R by utilizing the same methodology of [20]. Based on the framework, we further develop new constraints which characterize the unique placement and routing features of many-tier VFETs such as the absence of diffusion sharing and multiple stacking of transistors.…”

Section: Proposed Vfet Sdc Synthesis Frameworkmentioning

confidence: 99%

“…However, these approaches which rely on solving sub-problems are hard to reach the optimal cell-layout solution because of the intractable search space partitioning and the sub-optimal heuristic methodology. Recently, Lee et al [20] have proposed a Satisfiability Modulo Theories (SMT)-based SDC synthesis automation framework that simultaneously solves the place-and-route (P&R) problem without deploying any sequential procedures by using a novel dynamic pin allocation (DPA) approach, resulting in the generation of SDCs with optimal cell areas. However, this work is unsuitable for the VFET SDC generation due to the distinctive spatial cell structure.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Lee

Kang

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable PPAC (power, performance, area, and cost) benefits. In this paper, we propose a novel SMT (Satisfiability Modulo Theories)-based many-tier VFET standard cell (SDC) synthesis framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint and a dummy gate control scheme to capture the unique VFET cell architecture. Moreover, we present efficient objectives to improve pin-accessibility and reduce the use of vertical routing, which has high resistance. Compared to the conventional sequential P&R approach, our concurrent P&R achieves a 15.2% smaller cell area on average for 2tier VFET. Throughout the extensive exploration for many-tier VFET configurations up to 4-tier, we show that the 4-tier VFET respectively achieves 50.1% and 27.9% of average area reduction on chip-level and block-level, over 4.5T GAAFET.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: A Overview Of Vfet Sdc Synthesis Frameworkmentioning

confidence: 99%

Section: Proposed Vfet Sdc Synthesis Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Lee

Kang

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

Self Cite

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show abstract

Generalized Optimization Modulo Theories

Tsiskaridze,

Barrett,

Tinelli

2024

Lecture Notes in Computer Science

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Optimization Modulo Theories (OMT) has emerged as an important extension of the highly successful Satisfiability Modulo Theories (SMT) paradigm. The OMT problem requires solving an SMT problem with the restriction that the solution must be optimal with respect to a given objective function. We introduce a generalization of the OMT problem where, in particular, objective functions can range over partially ordered sets. We provide a formalization of and an abstract calculus for the Generalized OMT problem and prove their key correctness properties. Generalized OMT extends previous work on OMT in several ways. First, in contrast to many current OMT solvers, our calculus is theory-agnostic, enabling the optimization of queries over any theories or combinations thereof. Second, our formalization unifies both single- and multi-objective optimization problems, allowing us to study them both in a single framework and facilitating the use of objective functions that are not supported by existing OMT approaches. Finally, our calculus is sufficiently general to fully capture a wide variety of current OMT approaches (each of which can be realized as a specific strategy for rule application in the calculus) and to support the exploration of new search strategies. Much like the original abstract DPLL(T) calculus for SMT, our Generalized OMT calculus is designed to establish a theoretical foundation for understanding and research and to serve as a framework for studying variations of and extensions to existing OMT methodologies.

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Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

Cheng

Lee

et al. 2022

IEEE Access

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SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes

Cited by 16 publications

References 37 publications

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Generalized Optimization Modulo Theories

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

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