Some Like It Cold: Initial Testing Results for Cryogenic Computing Components

Kelly, T. K.; Fernández, Pedro Riesgo; Vogelsang, Thomas; McKee, Sally A.; Gopalakrishnan, Liji; Magee, S.; Padgett, Keith; Barrow, David A.; Rizza, Joseph; Doidge, Dennis; Wright, Kenneth L.; Hampel, Craig; Bronner, G.

doi:10.1088/1742-6596/1182/1/012004

Cited by 6 publications

(2 citation statements)

References 7 publications

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“…To alleviate some of the power and heat considerations that would be introduced by adding a large amount of semiconductor memory to the SCE system, the semiconductor memory could be implemented at an intermediate temperature. Cryogenic-DRAM is a technology that could potentially be used to fill this role in the system (Tannu et al, 2017;Ware et al, 2017;Wang et al, 2018;Kelly et al, 2019).…”

Section: Memory Hierarchymentioning

confidence: 99%

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

Tschirhart

Segall

2021

Front. Neurosci.

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Superconducting electronics (SCE) is uniquely suited to implement neuromorphic systems. As a result, SCE has the potential to enable a new generation of neuromorphic architectures that can simultaneously provide scalability, programmability, biological fidelity, on-line learning support, efficiency and speed. Supporting all of these capabilities simultaneously has thus far proven to be difficult using existing semiconductor technologies. However, as the fields of computational neuroscience and artificial intelligence (AI) continue to advance, the need for architectures that can provide combinations of these capabilities will grow. In this paper, we will explain how superconducting electronics could be used to address this need by combining analog and digital SCE circuits to build large scale neuromorphic systems. In particular, we will show through detailed analysis that the available SCE technology is suitable for near term neuromorphic demonstrations. Furthermore, this analysis will establish that neuromorphic architectures built using SCE will have the potential to be significantly faster and more efficient than current approaches, all while supporting capabilities such as biologically suggestive neuron models and on-line learning. In the future, SCE-based neuromorphic systems could serve as experimental platforms supporting investigations that are not feasible with current approaches. Ultimately, these systems and the experiments that they support would enable the advancement of neuroscience and the development of more sophisticated AI.

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Section: Memory Hierarchymentioning

confidence: 99%

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

Tschirhart

Segall

2021

Front. Neurosci.

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“…Cryogenic memories have been actively explored for (superconducting) high-performance computing [20], [21], [22], [23], [24], [25] and, more recently, for QC applications. From both perspectives, commercial DRAM memories have been investigated down to 77 K [26], [27], [28], [29], [30], [31]. However, for deep-cryogenic (4.2 K) applications, such as superconducting computing [32], [33], [34], [35], [36], [37], [38], [39] and QC, custom embedded memories have been investigated, including static-cell designs [10], [35], [36], [39], [40], [41], [42] and dynamic-cell designs [32], [43], [44], [45], [46], [47], [48], [49], [50].…”

Section: Introductionmentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

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The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-thresholdvoltage (LVT) DRAM at 4.2 K is up to 2× more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 000×, thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

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Interconnects Reliability for Future Cryogenic Memory Applications

Leong¹,

Huang²

2023

Springer Series in Reliability Engineering

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Some Like It Cold: Initial Testing Results for Cryogenic Computing Components

Cited by 6 publications

References 7 publications

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Interconnects Reliability for Future Cryogenic Memory Applications

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