Some Implications of MSC, SDL and TTCN Time Extensions for Computer-Aided Test Generation

Hogrefe, Dieter; Koch, Beat; Neukirchen, Helmut

doi:10.1007/3-540-48213-x_11

Cited by 7 publications

(13 citation statements)

References 10 publications

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“…Once the FSM is extracted [3], the time extensions for SDL [12] have a natural representation in our model (Section 4).…”

Section: Ma Fecko Initiated the Timed Efsm Modelmentioning

confidence: 99%

“…There are several classes of timers used in test sequences [12]: • global timers to assure that the execution of a test case stops even if it is blocked due to unexpected behavior of the SUT;…”

Section: Timing Modelmentioning

confidence: 99%

“…The delaying timers help the SUT reach a state where it can receive the next signal when a tester is too fast. They also help check the reaction of the SUT if a signal is delayed too long to test invalid behavior, e.g., to check that the SUT does not send any signal for a given amount of time [12]. We also consider another type of delaying timers, whose purpose is to help the SUT reach certain states that otherwise would become unreachable (Sections 4.3 and 4.4).…”

Section: Timing Modelmentioning

confidence: 99%

“…The timer mechanism in SDL is used to express timing behavior of a system with only one variable (Timer ) and three operations (Set, Stop and Expire) [12]. The passage of time is implicit and various background procedures handle timer set, stop, and expiry.…”

Section: Application To Sdlmentioning

confidence: 99%

“…Proper handling of timers is of special concern for computer-aided test generation from formal specifications [4,8,12,13,19,22]. Consider sending a message that requires an acknowledgment, which implies that two timers may be started with different expiry times.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

Fecko¹,

Duale²

2003

Formal Techniques for Networked and Distributed Systems - FORTE 2003

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Abstract.A recent model for testing systems with multiple timers is extended to compute proper input delays and timeout settings, and is applied to several types of timers required in a testing procedure. In the model, any transition in the specification can be made conditional on a set of running timers. Depending on the path taken to reach an edge, the values of the timer variables may render the traversal of the edge infeasible. The presented modeling technique, combined with the INconsistencies DEtection and ELimination (INDEEL) algorithms, allows the generation of feasible test sequences. The model also offers the flexibility to define timer lengths as variables, and have the INDEEL find the appropriate timer ranges. An approach to apply this new methodology to SDL timed extensions (guarding and delaying timers) is presented.

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“…Once the FSM is extracted [3], the time extensions for SDL [12] have a natural representation in our model (Section 4).…”

Section: Ma Fecko Initiated the Timed Efsm Modelmentioning

confidence: 99%

Section: Timing Modelmentioning

confidence: 99%

Section: Timing Modelmentioning

confidence: 99%

Section: Application To Sdlmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

Fecko¹,

Duale²

2003

Formal Techniques for Networked and Distributed Systems - FORTE 2003

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An Extension for MSC-2000 and Its Application

Zheng

Khendek

2003

Lecture Notes in Computer Science

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Abstract. Message Sequence Charts (MSC) is a standard language widely used in telecommunication software engineering. The latest MSC standard, MSC-2000, includes new features such as time and data. In this paper, we propose a new construct called instance delay as an extension for timed MSC to enhance further its expressiveness. We define formally the semantics of the extension based on a partial order semantics of timed MSC. We demonstrate through an application the need for this extension.

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A Guided Method for Testing Timed Input Output Automata

En‐Nouaary

Dssouli

2003

Lecture Notes in Computer Science

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Abstract. Real-time systems are those systems whose behaviors are time dependent. Reliability is one of the characteristics of such systems and testing is one of the techniques that can be used to ensure reliable real-time systems. This paper presents a method for testing real-time systems specified by Timed Input Output Automata (TIOA). Our method is based on the concept of test purposes. The use of test purposes helps reduce the number of test cases generated since an exhaustive testing of a TIOA causes the well-known state explosion problem. The approach we present in this paper consists of three main steps. First, a synchronous product of the specification and test purpose is computed. Then, a subautomaton (called Grid Automata) representing a subset of the state space of this product is derived. Finally, test cases are generated from the resulting grid automata. The test cases generated by our method are executable and can easily be represented in TTCN (Tabular Tree Combined Notation).

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Some Implications of MSC, SDL and TTCN Time Extensions for Computer-Aided Test Generation

Cited by 7 publications

References 10 publications

Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

An Extension for MSC-2000 and Its Application

A Guided Method for Testing Timed Input Output Automata

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