Solving Static and Dynamic Performance Limitations for High Speed D/A Converters

Bosch, A. Van den; Steyaert, Michiel; Sansen, Willy

doi:10.1007/0-306-47950-8_10

Cited by 7 publications

(9 citation statements)

References 22 publications

(32 reference statements)

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“…This places an upper bound on SFDR at frequencies near DC [5,6]. Thus, the INL can provide an estimate of the maximum SFDR before further degradation due to timing-and amplitude-related errors [2].…”

Section: Inl Induced Distortionmentioning

confidence: 99%

“…These include dividing the full scale voltage range by the number of quantization levels, using the end-points to generate a linear fit, or employing the best fit line. Owing to its simplicity, the end-point fit is the most preferred method to measure the DAC's offset [2]. The straightforward method to determine the DAC offset is by calculating the deviation between the real and ideal transfer functions when the binary input is all zeros.…”

Section: Offset and Gain Errorsmentioning

confidence: 99%

“…The choice of metrics depends on the desired application ranging from high precision systems such as potentiometers and medical instrumentation to waveform synthesis in high-speed communication systems. This section briefly introduces the commonly used metrics to characterize the DAC performance [2][3][4][5].…”

Section: Performance Metricsmentioning

confidence: 99%

See 2 more Smart Citations

Current and Emerging Trends in the Design of Digital-to-Analog Converters

Balasubramanian

Patel

Khalil

2013

Design, Modeling and Testing of Data Converters

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The advent of digital computing, coupled with the continued scaling of CMOS devices, has led to the rapid growth in theory and applications of digital signal processing (DSP). In order to leverage the available increase in speed, complexity, and integration, high-performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are needed to ensure the highest signal fidelity when moving between the analog and digital domains. Traditionally, high-speed ADCs have attracted more attention in the research and scientific community than their DAC counterparts, mainly due to the inherent shift towards receivers in the study and analysis of radio systems [1].This chapter aims to describe some of the design challenges and emerging trends for high-speed and high-resolution digital-to-analog converters. Section 3.1 presents an overview of the digital-to-analog conversion process. Section 3.2 delves into DAC characterization by outlining different sources of error and metrics used to quantify the DAC performance. A summary of DAC topologies and circuit limitations in the context of current-steering (CS) DACs is provided in Sects. 3.3 and 3.4, respectively. Section 3.5 details four major considerations in the design space of CS DACs. Realizing that the segmented architecture is the de facto standard in high-resolution DACs, a supplemental approach to segmentation is presented in Sect. 3.6. An in-depth survey of current and emerging architectural trends in high-performance DACs is discussed in Sect. 3.7. Finally, Sect. 3.8 concludes with a summary and a brief discussion on future directions.

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Section: Inl Induced Distortionmentioning

confidence: 99%

Section: Offset and Gain Errorsmentioning

confidence: 99%

See 1 more Smart Citation

Current and Emerging Trends in the Design of Digital-to-Analog Converters

Balasubramanian

Patel

Khalil

2013

Design, Modeling and Testing of Data Converters

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“…The cascode device (M1) plays a role of isolating the current source (M0) from the switches [43,44] , so as to avoid the influence of the parasitic capacitance of the current source on the fast switching differential pairs. At high fre-80 2015VLSI [38] 2018ISSCC [17] 2018JSSC [40] 2017ISSCC [36] 2012JSSC [11] 2016VLSI [37] 2014VLSI [39] 2018JSSC [40] 2012JSSC [11] 2020JSSC [35] Table 1. Performance summary and comparison with state-of-the-art high-speed high-resolution DACs.…”

Section: Switching Current Source Cell Designmentioning

confidence: 99%

A survey of high-speed high-resolution current steering DACs

Li¹,

Zhou²

2020

J. Semicond.

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Digital to analog converters (DAC) play an important role as a bridge connecting the analog world and the digital world. With the rapid development of wireless communication, wideband digital radar, and other emerging technologies, better performing high-speed high-resolution DACs are required. In those applications, signal bandwidth and high-frequency linearity often limited by data converters are the bottleneck of the system. This article reviews the state-of-the-art technologies of high-speed and high-resolution DACs reported in recent years. Comparisons are made between different architectures, circuit implementations and calibration techniques along with the figure of merit (FoM) results.

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“…The main drawback of the weighted binary CS-DAC design lies in the persistence of glitches due to the delays caused by the switch of varying currents. These glitches can well engender a reduction in the system's respective dynamic performance [38].…”

Section: Current Pulse Generator Design • Current Steering Digital-tomentioning

confidence: 99%

Design of High Output Impedance, Large Voltage Compliance Output Stage of Implantable Hypoglossal Nerve Stimulator (HGNS) for OSA Treatment

Salah¹,

Abbes²,

Abdelmoula³

et al. 2020

Adv. sci. technol. eng. syst. j.

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Obstructive Sleep Apnea (OSA) is a potentially common sleep disorder manifested in upper airways' collapse, either partially or completely. If diagnosed late and untreated, it may result in serious complications. The standard golden method, useful for treating OSA, remains the full night Continuous Positive Airway Pressure (CPAP). Yet, due to the ensuing discomfort it incurs on patients, researchers have been motivated to investigate other efficient alternatives, whereby, OSA can be effectively treated. More recently, an increasingly popular OSA treatment solution has been developed that consists in activating the protrusion muscles of the tongue by stimulating the Hypoglossal Nerve (HGN). After discussing the classification topologies of some neural stimulator output design stages, we consider putting forward the design of output stage of Hypoglossal Nerve Stimulator (HGNS), in compliance with the HGN requirements. The proposed HGNS is simulated in cadence software using the 0.35µm CMOS technology and Matlab software. It proved to enable the delivery of a maximum stimulation current of 1mA through 1kΩ resistive load under 3.3V voltage supply. The output stage managed to achieve large voltage compliance of 94% of the voltage supply and high output impedance of 275MΩ at full scale stimulus current. The total power consumption is about 705.87µW.

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Solving Static and Dynamic Performance Limitations for High Speed D/A Converters

Cited by 7 publications

References 22 publications

Current and Emerging Trends in the Design of Digital-to-Analog Converters

Current and Emerging Trends in the Design of Digital-to-Analog Converters

A survey of high-speed high-resolution current steering DACs

Design of High Output Impedance, Large Voltage Compliance Output Stage of Implantable Hypoglossal Nerve Stimulator (HGNS) for OSA Treatment

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