Solution-Processed Organic and ZnO Field-Effect Transistors in Complementary Circuits

Abstract

The use of high κ dielectrics lowers the operating voltage in organic field-effect transistors (FETs). Polymer ferroelectrics open the path not just for high κ values but allow processing of the dielectric films via electrical poling. Poled ferroelectric dielectrics in p-type organic FETs was seen to improve carrier mobility and reduce leakage current when compared to unpoled devices using the same dielectric. For n-type FETs, solution-processed ZnO films provide a viable low-cost option. UV–ozone-treated ZnO films was seen to improve the FET performance due to the filling of oxygen vacancies. P-type FETs were fabricated using the ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as the dielectric along with a donor–acceptor polymer based on diketopyrrolopyrrole (DPP-DTT) as the semiconductor layer. The DPP-DTT FETs yield carrier mobilities upwards of 0.4 cm2/Vs and high on/off ratios when the PVDF-TrFE layer is electrically poled. For n-type FETs, UV–ozone-treated sol–gel ZnO films on SiO2 yield carrier mobilities of 10−2 cm2/Vs. DPP-DTT-based p- and ZnO-based n-type FETs were used in a complementary voltage inverter circuit, showing promising characteristic gain. A basic inverter model was used to simulate the inverter characteristics, using parameters from the individual FET characteristics.

Molecularly Engineered Quinoxaline-Pyridyl Pyrazine Polymers for Field-Effect Transistors and Complementary Circuits

“…Using an analytical model by Bode et al, we have modeled the inverter characteristics of IID-TzSe and P1 . The inverter characteristics requires five different regions for modeling . The two extreme (regions 1 and 5) are (i) V in < V Th of the n-type FET, V out = V DD and (ii) V in > V Th (p-type) + V DD , V out = 0.…”

“…The inverter characteristics requires five different regions for modeling. 49 The two extreme (regions 1 and 5) are (i) V in < V Th of the ntype FET, V out = V DD and (ii) V in > V Th (p-type) + V DD , V out = 0. These two regions correspond to the p-type and n-type FETs being operational, respectively.…”