SOI monolithic pixel technology for radiation image sensor

Arai, Y.; Miyoshi, T.; Kurachi, Ikuo

doi:10.1109/iedm.2017.8268401

Cited by 6 publications

(3 citation statements)

References 8 publications

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“…The active merge technique can reduce the circuit area, for example, the area of a standard D-type flip-flop becomes 16.5% [14]. The SOI is tolerant against neutrons and single event upset.…”

Section: Soi Technologymentioning

confidence: 99%

“…Large-surface-area detector panels of about 3.1-cm thickness are sandwiched in the gaps between the steel plates of the solenoid's magnetic-field flux return. Each panel contains either RPCs (barrel layers [3][4][5][6][7][8][9][10][11][12][13][14][15] or scintillator strips (barrel layers 1-2, forward-endcap layers 1-14 and backward-endcap layers 1-12). The RPC cathode readout strips are about 4 cm wide and each scintillator strip is 4 cm wide, measured orthogonal to a line from the SuperKEKB e + e − collider's interaction point (IP); this matches the Molière radius of muons originating at the interaction point and traversing the electromagnetic calorimeter located just inside the solenoid.…”

Section: Klm Geometry and Instrumentationmentioning

confidence: 99%

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Snowmass Whitepaper: The Belle II Detector Upgrade Program

Forti¹

2022

Preprint

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We describe the planned near-term and potential longer-term upgrades of the Belle II detector at the SuperKEKB electron-positron collider in Tsukuba, Japan. These upgrades will allow increasingly sensitive searches for possible new physics beyond the Standard Model in flavor, tau, electroweak and dark sector physics that are both complementary to and competitive with the LHC and other experiments. We encourage the instrumentation-frontier community to contribute and study upgrade ideas as part of the Snowmass process.

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Section: Soi Technologymentioning

confidence: 99%

Section: Klm Geometry and Instrumentationmentioning

confidence: 99%

Snowmass Whitepaper: The Belle II Detector Upgrade Program

Forti¹

2022

Preprint

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“…Evaluation of the X-CHIP-02 [1] detection capabilities and its performance in irradiation tests showed that the SOI CMOS technology is promising not only in the field of soft X-ray imaging, but also in charged particle detection [2]. The X-CHIP-03 [3] is an evolution of the X-CHIP-02 design, with slightly larger pixels, inter-pixel and global architecture improvements and an additional functionality of signal amplitude measurement.…”

Section: Introductionmentioning

confidence: 99%

TID and SEU testing of the novel X-CHIP-03 monolithic pixel detector

et al. 2020

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A: We present a SEE and TID effect study of the novel monolithic pixel detector, X-CHIP-03, manufactured in a 180 nm SOI technology. The SEU cross section of the custom D flip-flops in the X-CHIP-03 ASIC has been evaluated using accelerated ions with LET ranging from 0.45 to 69 MeV•cm 2 •mg −1 . The global TID response of the X-CHIP-03 has been evaluated at a dose rate of 16.2 Gy•min −1 . The direct I-V measurements of transistor properties were made under identical radiation conditions using the predecessor X-CHIP-02 ASIC manufactured in the same technology, which contains the transistor testing matrices for TID measurements. K: Radiation damage to detector materials (solid state); Radiation damage to electronic components; Radiation-hard detectors; Radiation-hard electronics 1Corresponding author.

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