Soi Materials

Colinge, Jean–Pierre

doi:10.1007/978-1-4419-9106-5_2

Cited by 10 publications

(11 citation statements)

References 125 publications

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“…It must be emphasized that the form of this model is almost identical to that of SOI models [29]. This should not be surprising, given that in both cases the kink results from similar physics-impact ionization, hole accumulation, and a Boltzmann-type relationship relating potential to hole accumulation.…”

Section: Equivalent Circuit Modelmentioning

confidence: 57%

“…This should not be surprising, given that in both cases the kink results from similar physics-impact ionization, hole accumulation, and a Boltzmann-type relationship relating potential to hole accumulation. It is important to note, though, that the detailed physical origins of the kink in the two models are significantly different-in partially-depleted SOI, the kink arises from forward biasing the source-body junction [29], whereas in this model, the kink is a result of hole accumulation in the extrinsic source and the ensuing modification of the channel potential and electron concentration beneath the source end of the gate. While this difference has no impact on the form of the model, it is an important consideration when one attempts to engineer away the kink-if the kink is due to a floating body effect, one might try to suppress it by introducing an additional barrier in the valence band beneath the channel, or by increasing the resistivity of the buffer.…”

Section: Equivalent Circuit Modelmentioning

confidence: 96%

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A new physical model for the kink effect on InAlAs/InGaAs HEMTs

Somerville

Alamo

Hoke³

Proceedings of International Electron Devices Meeting

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Abstract-We present a new model for the the kink effect in InAlAs/InGaAs HEMT's. The model suggests that the kink is due to a threshold voltage shift which arises from a hole pile-up in the extrinsic source and an ensuing charging of the surface and/or the buffer-substrate interface. The model captures the many of the observed behaviors of the kink, including the kink's dependence on bias, time, temperature, illumination, and device structure. Using the model, we have developed a simple equivalent circuit, which reproduced well the kink's dc characteristics, its time evolution in the nanosecond range, and its dependence on illumination.

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Section: Equivalent Circuit Modelmentioning

confidence: 57%

Section: Equivalent Circuit Modelmentioning

confidence: 96%

A new physical model for the kink effect on InAlAs/InGaAs HEMTs

Somerville

Alamo

Hoke³

Proceedings of International Electron Devices Meeting

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“…Besides obvious reliability issues, the lowering of the operating temperature greatly impacts device performance. 8,14 The carrier mobility is dominated by acoustic phonon scattering and varies approximately as ϳ T Ϫ1. 5 .…”

Section: Thermal Advantages Of Buried Aluminamentioning

confidence: 99%

“…The outstanding advantage of SOI MOSFETs is that the body overdoping becomes unnecessary, as CSE and DIBL are suppressed simply, by using thin enough films. 5,14,15 Because these effects occur in the transistor body, the properties of the buried insulator ͑thickness and dielectric constant͒ have a second-order impact. Unfortunately, thin SOI MOSFETs are prone to another shortchannel mechanism: drain-induced virtual substrate biasing ͑DIVSB͒.…”

Section: Short Channel Effects: Fringing Fields In Buried Aluminamentioning

confidence: 99%

SOI MOSFETs with Buried Alumina: Thermal and Electrical Aspects

Oshima¹,

Cristoloveanu²,

Guillaumot³

et al. 2004

J. Electrochem. Soc.

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To improve thermal dissipation in silicon-on-insulator metal-oxide-semiconductor field-effect transistors ͑SOI MOSFETs͒, we recently proposed replacing the buried oxide with buried alumina, which offers higher thermal conductivity. However, because alumina is a high-k insulator, there is also a definite impact on the electrical properties, namely, coupling and short-channel effects. Our simulations show that the role of fringing fields is accentuated, leading to more severe drain-induced barrier lowering ͑DIBL͒-like problems. The trade-off between the thermal merit and the electrical performance of very advanced SOI transistors is examined by comparing various MOS architectures. We conclude on the usefulness of a ground plane located underneath a relatively thin buried alumina.Silicon-on-insulator ͑SOI͒ technology has been included in the International Technology Roadmap of Semiconductors ͑ITRS͒ for two reasons: ͑i͒ enhanced performance of high-speed and/or lowpower complementary metal-oxide-semiconductor ͑CMOS͒ circuits and (ii) superior scalability. The future of bulk-Si MOS field-effect transistors ͑FETs͒ is unfortunately blocked by the necessity to continuously increase the doping level and reduce the junction thickness. The scaling rules are totally different for fully depleted SOI transistors, where the thin silicon film and buried oxide ͑BOX͒ can serve as additional tunable parameters. 1-5 The film thickness actually plays the dominant role and offsets the importance of film doping.The optimum film thickness is roughly one-third of the channel length. 6,7 This condition allows controlling the short-channel effects: threshold voltage roll-off, drain-induced barrier lowering ͑DIBL͒, subthreshold swing degradation, etc. A very thin Si film, t Si ϭ 5-15 nm only, is therefore required in deeply scaled SOI MOSFETs with 20-50 nm gate length.The problem with thinner Si films is that they aggravate the self-heating of SOI devices. The heat path through the source/drain regions is squeezed which increases the thermal resistance and causes the temperature to rise in the transistor body, as shown in Fig. 1. Self-heating in SOI MOSFETs is responsible for degradation in mobility, threshold voltage, subthreshold swing, leakage current, etc. 8 Because self-heating is due mainly to the poor thermal conductivity of the buried SiO 2 , an innovative solution we have proposed recently 9,10 is to replace the BOX with buried alumina or other dielectric, able to offer much improved thermal conductivity. The resulting structure is still SOI ͑thin Si-film, highly thermal conductive insulator, Si substrate͒, with the last letter of the acronym SOI becoming more meaningful. Such a material can be synthesized by adapting the current bonding techniques. 10 There are three basic steps: ͑i͒ alumina growth on a silicon wafer by atomic layer deposition, (ii) bonding to a passive wafer, and (iii) film thinning by Smart-Cut process or etchback. Prototype SOI structures with buried alumina have been manufactured and preliminary characterizat...

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“…The FinFET is one of the most promising multiple-gate alternative structures for scaling down MOS technology, because of its better current drive and smaller shortchannel effects (1). Due to limitations of process uniformity, some fabricated FinFETs have width variation along the vertical direction, resulting in several fin cross-section shapes, other than the designed rectangular shape.…”

Section: Introductionmentioning

confidence: 99%

Non-Vertical Sidewall Angle Influence on Triple-Gate FinFETs Corner Effects

Giacomini¹,

Martino²

2007

ECS Trans.

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Some fabricated FinFET devices present width variations along the vertical direction due to fabrication process limitations. These variations lead to non-rectangular cross-section shapes. One of the most frequent shapes is the trapezoidal (plane and inclined sidewalls). Another identified phenomenon in multiple- gate devices such as FinFETs is the corner effect, which occurs due to the overlapping of the influences of two gate planes near the device corners. This paper addresses the variation of the corner effect as a function of the sidewall inclination angle, through 3-D numeric simulation. A set of devices of several inclination angles and body doping levels were simulated. The corner effect depends on the inclination angle, specially for higher doping levels.

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Soi Materials

Cited by 10 publications

References 125 publications

A new physical model for the kink effect on InAlAs/InGaAs HEMTs

A new physical model for the kink effect on InAlAs/InGaAs HEMTs

SOI MOSFETs with Buried Alumina: Thermal and Electrical Aspects

Non-Vertical Sidewall Angle Influence on Triple-Gate FinFETs Corner Effects

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