Software-Implemented Fault Injection of Transient Hardware Errors

Abstract

As computer applications extend to areas which require extreme dependability, their designs mai\date the ability to operate in the presence of faults. The problem of assuring that the design goals are achieved requires the observation and measurement of fault behavior parameters under various input conditions. One means to characterize systems is fault injection, but injection of internal faults is difficult due to the complexity and level of integration of contemporary VLSI implementations. This chapter explores the effects of gate-level faults on system operation as a basis for fault models at the program level.A new fault model for processors based on a register-transfer-level (RTL) description is presented. This model addresses time, cost, and accuracy limitations imposed by current fault-injection techniques. It is designed to be used with existing software-implemented fault-injection (SWIFT) tools, but the error patterns it generates are designed to be more representative of actual transient hardware faults than the ad-hoc patterns currently injected via most SWIFI experiments. INTRODUCTIONAs persons become more and more dependent on computers in everyday life, and, in many cases, for life itself, the understanding of how those computers react to faults becomes more important [13], Today's systems are much too complex to use purely formal techniques to prove their correctness, much less to prove that recovery from faults is performed correctly. Also, present technology produces parts with mean times to failure (MTTF) of several years, so designers cannot 'The research described in this chapter was funded in part by the Office of Naval Research under grant N00014-91-J-4139. ^Inter